Datasheet
Data Sheet AD9287
Rev. E | Page 39 of 52
CSB
C217
0.1µF
C220
0.1µF
C221
0.1µF
C218
0.1µF
C219
0.1µF
C223
0.1µF
C222
0.1µF
AVDD_3.3V
CLK
CLKB
GND
GND_PAD
OUT0
OUT0B
OUT1
OUT1B
RSET
S0
S1
S10
S2
S3
S4
S5
S6
S7
S8
S9
SYNCB
VREF
VS
SIGNAL = DNC;27,28
INPUT
ENCODE
ENC
ENC
DNP
CLOCK CIRCUIT
OPTIONAL CLOCK DRIVE CIRCUIT
DISABLE
ENABLE
OPTIONAL CLOCK
OSCILLATOR
C224
0.1µF
R214
10kΩ
R215
10kΩ
14
78
1
3
5
12
10
OSC201
VFAC3H-L
C207
0.1µF
DNP
C208
0.1µF
DNP
C209
0.1µF
DNP
C215
0.1µF
DNP
C211
0.1µF
C210
0.1µF
E202
1
E201
P201
P203
AVDD_3.3V
12
6
7
25
8
16
9
15
10
14
11
13
18
19
23
22
32
1
31
33
U202
SIGNAL = AVDD_3.3V;4,17,20,21,24,26,29,30
AD9515
3
2
1
CR201
HSMS2812
R220
DNP
R240
243Ω
R243
100Ω
R241
243Ω
R242
100Ω
6
5
43
2
1
T201
1
2
J205
C205
0.1µF
C216
0.1µF
R213
49.9kΩ
R216
0Ω
R221
10kΩ
R212
0Ω
DNP
R219
DNP
S0S1S2S3S4S5S6S7S8S9S10
OPT_CLK
OPT_CLK
CLK
AVDD_3.3V
OPT_CLK
OPT_CLK
CLK
CLK
LVPECL OUTPUT
LVDS OUTPUT
CLK
AVDD_3.3V
1
1
E203
AVDD_3.3V
VCC
GNDOUT
OE
OE'
GND'
VCC'
OUT'
R244
DNP
R245
0Ω
S4
S0
S5
S3
S2
S1
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
R246
DNP
R247
0Ω
R248
DNP
R249
0Ω
R250
DNP
R251
0Ω
R252
DNP
R253
0Ω
R254
DNP
R255
0Ω
R256
DNP
R257
0Ω
S10
S6
S9
S8
S7
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
R258
DNP
R259
0Ω
R260
DNP
R261
0Ω
R262
DNP
R263
0Ω
R264
DNP
R265
0Ω
A1
A2
A3
A4
A5
A6
A7
A8
A9
GNDAB1
GNDAB10
GNDAB2
GNDAB3
GNDAB4
GNDAB5
GNDAB6
GNDAB7
GNDAB8
GNDAB9
GNDCD1
GNDCD10
GNDCD2
GNDCD3
GNDCD4
GNDCD5
GNDCD6
GNDCD7
GNDCD8
GNDCD9
HEADER 6469169-1
R205 TO R211
OPTIONAL OUTPUT
TERMINATIONS
DIGITAL OUTPUTS
CSB3_CHB
SDI_CHB
SDO_CHA
CSB2_CHA
CSB1_CHA
SDI_CHA
SCLK_CHA
R206
DNP
R211
DNP
R210
DNP
R209
DNP
R208
DNP
P202
R207
DNP
SCLK_CHB
DCO
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C10
50
49
48
47
46
45
44
43
42
41
20
19
18
17
16
15
14
13
12
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
11
CHD
CHC
CHB
CHA
FCO
DCO
CHD
CHC
CHB
CHA
FCO
SDO_CHB
CSB4_CHB
40
60
1
9
21
22
4
5
25
6
26
8
31
32
33
34
35
36
37
38
29
10
30
2
23
3
24
28
51
52
53
54
55
56
57
58
39
59
7
27
ODM ENABLE
CLK
AVDD
CLK+
CLK–
D + A
D + B
D + C
D + D
D – A
D – B
D – C
D – D
DCO+
DCO–
DRVDD
DRGND
FCO+
FCO–
PDWN
RBIAS
REFB
REFT
SCLK/DTP
SDIO/ODM
SENSE
VIN + A
VIN + B
VIN + C
VIN + D
VIN – A
VIN – B
VIN – C
VIN – D
VREF
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
DRGND
DRVDD
REFERENCE
DECOUPLING
C204
0.1µF
C203
0.1µF
C202
2.2µF
C201
0.1µF
R205
10kΩ
R203
100kΩ
R204
100kΩ
3
2
2
2
2
1
J201
1
8
7 30
20
18
16
14
19
17
15
13
24
23
11
12
22
21
10
2
25
26
27
32
35
36
39
45
46
5
6
9
31
40
43
44
28
29
41
33
38
47
4
34
37
48
3
42
U201
AD9287 LFCSP
R202
100kΩ
CSB_DUT
1
3
J202
SDIO_ODM
1
3
J203
SCLK_DTP
3
1
J204
DRVDD_DUT DRVDD_DUT
R201
10kΩ
AVDD_DUT
CHA
CHB
CHC
CHD
CHA
CHB
CHC
DCO
DCO
FCO
FCO
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
VSENSE_DUT
VIN_A
VIN_B
VIN_C
VIN_A
VIN_B
VREF_DUT
AVDD_DUT
AVDD_DUT
CLK
CHD
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
VIN_D
VIN_C
VIN_D
GNDGND
AVDD_DUT
PWDN ENABLE
ALWAYS ENABLE SPI
DTP ENABLE
U203
CW
VREF = 1V
VREF = EXTERNAL
VREF = 0.5V
REMOVE C214 WHEN USING EXTERNAL VREF
VREF = 0.5V(1+R232/R233)
VREF SELECT
REFERENCE CIRCUIT
C212
0.1µF
R229
4.99kΩ
C214
1µF
C213
0.1µF
R230
10kΩ
R231
DNP
DNP
VSENSE_DUT
R228
470kΩ
DNP
DNP
R234
DNP
R235
DNP
R236
DNP
R237
0Ω
DNP
AVDD_DUT
VREF_DUT
AVDD_DUT
TRIM/NC
V–
V+
ADR510
1V
R232
DNP
R233
DNP
R217
0Ω
R218
0Ω
R225
0Ω
DNP
R226
49.9Ω
DNP
R227
0Ω
DNP
R238
DNP
R239
10kΩ
C206
0.1µF
R223
0Ω
R224
0Ω
R222
4.02kΩ
2
3
5
NC = NO CONNECT
R266
100kΩ - DNP
R267
100kΩ - DNP
CLIP SINE OUT (DEFAULT)
DNP: DO NOT POPULATE
OPTIONAL
EXT REF
05966-016
Figure 63. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface