Datasheet

AD9287 Data Sheet
Rev. E | Page 6 of 52
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter
1
Temp Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage
2
Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance
25°C
1.5
pF
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 70 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage Full 1.2 DRVDD + 0.3 V
Logic 0 Voltage
Full
0
0.3
V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC OUTPUT (SDIO/ODM)
3
Logic 1 Voltage (I
OH
= 800 μA) Full 1.79 V
Logic 0 Voltage (I
OL
= 50 μA) Full 0.05 V
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance LVDS
Differential Output Voltage (V
OD
) Full 247 454 mV
Output Offset Voltage (V
OS
) Full 1.125 1.375 V
Output Coding (Default) Offset binary
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal Option)
Logic Compliance LVDS
Differential Output Voltage (V
OD
) Full 150 250 mV
Output Offset Voltage (V
OS
)
Full
1.10
1.30
V
Output Coding (Default) Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO pins sharing the same connection.