Datasheet

Data Sheet AD9287
Rev. E | Page 7 of 52
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter
1, 2
Temp Min Typ Max Unit
CLOCK
3
Maximum Clock Rate Full 100 MSPS
Minimum Clock Rate Full 10 MSPS
Clock Pulse Width High (t
EH
) Full 5 ns
Clock Pulse Width Low (t
EL
) Full 5 ns
OUTPUT PARAMETERS
3
Propagation Delay (t
PD
) Full 2.0 2.7 3.5 ns
Rise Time (t
R
) (20% to 80%) Full 300 ps
Fall Time (t
F
) (20% to 80%) Full 300 ps
FCO Propagation Delay (t
FCO
) Full 2.0 2.7 3.5 ns
DCO Propagation Delay (t
CPD
)
4
Full t
FCO
+
(t
SAMPLE
/16)
ns
DCO to Data Delay (t
DATA
)
4
Full (t
SAMPLE
/16) − 300 (t
SAMPLE
/16) (t
SAMPLE
/16) + 300 ps
DCO to FCO Delay (t
FRAME
)
4
Full (t
SAMPLE
/16) − 300 (t
SAMPLE
/16) (t
SAMPLE
/16) + 300 ps
Data to Data Skew
(t
DATA-MAX
− t
DATA-MIN
)
Full ±50 ±150 ps
Wake-Up Time (Standby) 25°C 600 ns
Wake-Up Time (Power-Down) 25°C 375 μs
Pipeline Latency Full 8 CLK cycles
APERTURE
Aperture Delay (t
A
) 25°C 500 ps
Aperture Uncertainty (Jitter) 25°C <1 ps rms
Out-of-Range Recovery Time
25°C
2
CLK cycles
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
2
Measured on standard FR-4 material.
3
Can be adjusted via the SPI.
4
t
SAMPLE
/16 is based on the number of bits multiplied by 2; delays are based on half duty cycles.