AD9481
Rev. 0 | Page 7 of 28
TIMING DIAGRAM
05045-002
INTERLEAVED DATA OUT
VIN
CLK+
CLK–
D7A TO D0
PORT A
STATIC INVALID N
N–1
N+1
8 CYCLES
N+7
N+8
N+9
N+10
N
D7B TO D0B
PORT B
STATIC INVALID INVALID N+1
t
V
t
PD
t
EH
DS+
DS–
t
HDS
t
SDS
t
A
t
EL
1/f
S
DCO+
DCO–
STATIC
t
CPD
t
SKA
t
SKB
Figure 2. Timing Diagram
