Datasheet

Evaluation Board User Guide UG-290
Rev. 0 | Page 5 of 28
20kΩ
NOT USED
SPI CTRL VREF SELECT
00: INTERNAL VREF
01: IMPORT VREF
10: EXPORT VREF
11: NOT USED
(01)
(10)
(00)
AVDD
VREF
(11)
09910-004
Figure 4. Equivalent VREF Input/Output Circuit
Clock Circuitry for the AD9434/AD9484
The default clock input circuit on the evaluation board uses a
simple transformer-coupled circuit using a high bandwidth
1:1 impedance ratio transformer (T201) that adds a low amount of
jitter to the clock path. The clock input is 50 Ω terminated and ac-
coupled to handle single-ended sine wave types of inputs. The
transformer converts the single-ended input to a differential signal
that is clipped by CR200 before entering the ADC clock inputs.
The evaluation board is by default set up to be clocked with the
transformer-coupled input network connected to the external
clock source through the SMA connector, J200 (labeled CLK+).
PDWN
To enable the power-down feature, add a shorting jumper across
P200 at Pin 1 and Pin 2 to connect the PDWN pin to AVDD.
Table 1. Register 0x18 Settings
Address
(Hexadecimal) Parameter Name Bits[7:6] Bit 5 Bits[4:0]
0x18 Input range VREF select
1
00 = internal V
REF
(20 kΩ pull-down internally)
01 = import V
REF
(apply 0.59 V to 0.8 V to Pin 31)
10 = export V
REF
(monitor)
11 = not used
0 Input voltage range setting (V)
11100 = 1.60
11101 = 1.58
11110 = 1.55
11111 = 1.52
00000 = 1.50
00001 = 1.47
00010 = 1.44
00011 = 1.42
00100 = 1.39
00101 = 1.36
00110 = 1.34
00111 = 1.31
01000 = 1.28
01001 = 1.26
01010 = 1.23
01011= 1.20
01100 = 1.18
1
VREF x 2 = input range.