Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9510BCPZ

1.2 GHz Clock Distribution IC, PLL Core,

Dividers, Delay Adjust, Eight Outputs

Data Sheet

AD9510

Rev. B Document Feedback

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FEATURES

Low phase noise phase-locked loop core

Reference input frequencies to 250 MHz

Programmable dual modulus prescaler

Programmable charge pump (CP) current

Separate CP supply (VCP

) extends tuning range

Two 1.6 GHz, differential clock inputs

8 programmable dividers, 1 to 32, all integers

Phase select for output-to-output coarse delay adjust

4 independent 1.2 GHz LVPECL outputs

Additive output jitter of 225 fs rms

4 independent 800 MHz low voltage differential signaling

(LVDS) or 250 MHz complementary metal oxide conductor

(CMOS) clock outputs

Additive output jitter of 275 fs rms

Fine delay adjust on 2 LVDS/CMOS outputs

Serial control port

Space-saving 64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and

mixed-signal front ends (MxFEs)

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD9510 provides a multi-output clock distribution function

along with an on-chip phase-locked loop (PLL) core. The design

emphasizes low jitter and phase noise to maximize data converter

performance. Other applications with demanding phase noise

and jitter requirements also benefit from this device.

The PLL section consists of a programmable reference divider

(R); a low noise, phase frequency detector (PFD); a precision

charge pump (CP); and a programmable feedback divider (N).

By connecting an external voltage-controlled crystal oscillator

(VCXO) or voltage-controlled oscillator (VCO) to the CLK2

and CLK2B pins, frequencies of up to 1.6 GHz can be synchronized

to the input reference.

There are eight independent clock outputs. Four outputs are low

voltage positive emitter-coupled logic (LVPECL) at 1.2 GHz,

and four are selectable as either LVDS (800 MHz) or CMOS

(250 MHz) levels.

Each output has a programmable divider that can be bypassed

or set to divide by any integer up to 32. The phase of one clock

output relative to another clock output can be varied by means

of a divider phase select function that serves as a coarse timing

adjustment. Two of the LVDS/CMOS outputs feature program-

mable delay elements with full-scale ranges up to 8 ns of delay.

This fine tuning delay block has 5-bit resolution, giving 25

possible delays from which to choose for each full-scale setting

(Register 0x36 and Register 0x3A = 00000b to 11000b).

The AD9510 is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9510 is available in a 64-lead LFCSP and can be operated

from a single 3.3 V supply. An external VCO, which requires an

extended voltage range, can be accommodated by connecting

the charge pump supply (VCP) to 5.5 V. The temperature range

is −40°C to +85°C.

05046-001

R DIVIDER

N DIVIDER

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

PLL

SETTINGS

CLK2

STATUS

CLK2B

PROGRAMMABLE

DIVIDERS AND

PHASE ADJUST

OUT7

OUT7B

LVDS/CMOS

/1, /2, /3... /31, /32

OUT6

OUT6B

LVDS/CMOS

/1, /2, /3... /31, /32

OUT0

OUT0B

LVPECL

/1, /2, /3... /31, /32

OUT1

OUT1B

LVPECL

/1, /2, /3... /31, /32

OUT2

OUT2B

LVPECL

/1, /2, /3... /31, /32

OUT3

OUT3B

LVPECL

/1, /2, /3... /31, /32

OUT4

OUT4B

LVDS/CMOS

/1, /2, /3... /31, /32

OUT5

OUT5B

LVDS/CMOS

/1, /2, /3... /31, /32

∆

CLK1

CLK1B

REFIN

REFINB

FUNCTION

SCLK

SDIO

SDO

CSB

SERIAL

CONTROL

PORT

CPRSET

DISTRIBUTION

REF

SYNCB,

RESETB

PDB

RSET

AD9510

GNDVS

VCP

PLL

REF

Summary of content (56 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual modulus prescaler Programmable charge pump (CP) current Separate CP supply (VCPS) extends tuning range Two 1.6 GHz, differential clock inputs 8 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 4 independent 1.
PAGE 2
AD9510 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overall ......................................................................................... 28 Applications ....................................................................................... 1 PLL Section ................................................................................. 28 Functional Block Diagram ......................................
PAGE 3
Data Sheet AD9510 5/05—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to Table 1 and Table 2 ....................................................... 5 Changes to Table 4 ............................................................................ 8 Changes to Table 5 ............................................................................ 9 Changes to Table 6 .....................................................................
PAGE 4
AD9510 Data Sheet SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%, VS ≤ VCPS ≤ 5.5 V, TA = 25°C, RSET = 4.12 kΩ, CPRSET = 5.1 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. PLL CHARACTERISTICS Table 1.
PAGE 5
Data Sheet AD9510 Parameter NOISE CHARACTERISTICS In-Band Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) At 50 kHz PFD Frequency At 2 MHz PFD Frequency At 10 MHz PFD Frequency At 50 MHz PFD Frequency PLL Figure of Merit Min Typ Max Unit Test Conditions/Comments Synthesizer phase noise floor estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value) −172 −156 −149 −142 −218 + 10 × log (f
PAGE 6
AD9510 Data Sheet CLOCK OUTPUTS Table 3. Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2, OUT3; Differential Output Frequency Output High Voltage Output Low Voltage Output Differential Voltage LVDS CLOCK OUTPUTS OUT4, OUT5, OUT6, OUT7; Differential Output Frequency Differential Output Voltage Delta VOD Output Offset Voltage Delta VOS Short-Circuit Current CMOS CLOCK OUTPUTS OUT4, OUT5, OUT6, OUT7 Output Frequency Output Voltage High Output Voltage Low Symbol Min Typ Max Unit VOH VOL VOD VS − 1.
PAGE 7
Data Sheet Parameter PROPAGATION DELAY, CLK-TO-LVDS OUT1 OUT4, OUT5, OUT6, OUT7 Divide = Bypass Divide = 2 − 32 Variation with Temperature OUTPUT SKEW, LVDS OUTPUTS OUT4 to OUT7 on Same Part2 OUT5 to OUT6 on Same Part2 All LVDS OUTs on Same Part2 All LVDS OUTs Across Multiple Parts3 Same LVDS OUT Across Multiple Parts3 CMOS Output Rise Time Output Fall Time PROPAGATION DELAY, CLK-TO-CMOS OUT1 Divide = Bypass Divide = 2 − 32 Variation with Temperature OUTPUT SKEW, CMOS OUTPUTS All CMOS OUTs on Same Part2 All
PAGE 8
AD9510 Data Sheet CLOCK OUTPUT PHASE NOISE Table 5. Parameter CLK1-TO-LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 38.
PAGE 9
Data Sheet Parameter CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT= 622.08 MHz Divide Ratio = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset CLK1 = 491.52 MHz, OUT = 245.
PAGE 10
AD9510 Parameter CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset CLK1-TO-CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset CLK1 = 245.76 MHz, OUT = 61.
PAGE 11
Data Sheet AD9510 CLOCK OUTPUT ADDITIVE TIME JITTER Table 6. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT3) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT3) = 155.
PAGE 12
AD9510 Parameter CLK1 = 400 MHz LVDS (OUT4, OUT7) = 100 MHz Divide Ratio = 4 All Other LVDS = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT5, OUT6) = 100 MHz Divide Ratio = 4 All Other LVDS = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4, OUT7) = 100 MHz Divide Ratio = 4 All Other CMOS = 50 MHz (B Outputs Off ) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT5, OUT6) = 100 MHz Divide Ratio = 4 All Other CMOS = 50 MHz (B Outputs Off ) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4, OUT7) = 100 MHz Di
PAGE 13
Data Sheet AD9510 Parameter CLK1 = 400 MHz Min Typ 555 Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz All Other CMOS = 50 MHz (B Output On) DELAY BLOCK ADDITIVE TIME JITTER 1 100 MHz Output Delay FS = 1 ns (1600 μA, 1C) Fine Adjust 00000 Delay FS = 1 ns (1600 μA, 1C) Fine Adjust 11000 Delay FS = 2 ns (800 μA, 1C) Fine Adjust 00000 Delay FS = 2 ns (800 μA, 1C) Fine Adjust 11000 Delay FS = 3 ns (800 μA, 4C) Fine Adjust 00000 Delay FS = 3 ns (800 μA, 4C) Fine Adjust 1
PAGE 14
AD9510 Data Sheet Parameter SDIO (WHEN INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High, tPWH Pulse Width Low, tPWL SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CSB to SCLK Setup and Hold, tS, tH CSB Minimum Pulse Width High, tPWH Min Typ Max 2.0 0.8 10 10 2 2.7 0.
PAGE 15
Data Sheet AD9510 POWER Table 11. Parameter POWER-UP DEFAULT MODE POWER DISSIPATION Min Typ 550 Max 600 Unit mW Power Dissipation 1.1 W Power Dissipation 1.3 W Power Dissipation 1.
PAGE 16
AD9510 Data Sheet TIMING DIAGRAMS DIFFERENTIAL tCLK1 CLK1 80% LVDS tRL tFL 05046-065 20% tPECL 05046-002 tLVDS tCMOS Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode Figure 4. LVDS Timing, Differential DIFFERENTIAL SINGLE-ENDED 80% 80% LVPECL CMOS 3pF LOAD tRP tFP tRC Figure 3. LVPECL Timing, Differential tFC Figure 5. CMOS Timing, Single-Ended, 3 pF Load Rev.
PAGE 17
Data Sheet AD9510 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 12. Parameter VS to GND VCP to GND VCP to VS REFIN, REFINB to GND RSET to GND CPRSET to GND CLK1, CLK1B, CLK2, CLK2B to GND CLK1 to CLK1B CLK2 to CLK2B SCLK, SDIO, SDO, CSB to GND OUT0, OUT1, OUT2, OUT3 to GND OUT4, OUT5, OUT6, OUT7 to GND FUNCTION to GND STATUS to GND Junction Temperature1 Storage Temperature Lead Temperature (10 sec) 1 Value −0.3 V to +3.6 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.
PAGE 18
AD9510 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VS CPRSET GND RSET VS VS OUT0 OUT0B VS GND OUT1 OUT1B VS VS GND GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD9510 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VS OUT4 OUT4B VS VS OUT5 OUT5B VS VS OUT6 OUT6B VS VS OUT2 OUT2B VS NOTES 1. THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION AS WELL AS A THERMAL ENHANCEMENT.
PAGE 19
Data Sheet Pin No. 28 29 34 35 38 39 42 43 46 47 53 54 57 58 61 63 AD9510 Mnemonic OUT3B OUT3 OUT2B OUT2 OUT6B OUT6 OUT5B OUT5 OUT4B OUT4 OUT1B OUT1 OUT0B OUT0 RSET CPRSET EPAD Description Complementary LVPECL Output. LVPECL Output. Complementary LVPECL Output. LVPECL Output. Complementary LVDS/Inverted CMOS Output. OUT6 includes a delay block. LVDS/CMOS Output. OUT6 includes a delay block. Complementary LVDS/Inverted CMOS Output. OUT5 includes a delay block. LVDS/CMOS Output. OUT5 includes a delay block.
PAGE 20
AD9510 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.3 0.8 4 LVPECL + 4 LVDS (DIV ON) 0.7 4 LVPECL + 4 LVDS (DIV BYPASSED) 1.2 POWER (W) 0.5 DEFAULT–3 LVPECL + 2 LVDS (DIV ON) 0.4 4 LVDS ONLY (DIV ON) 0.3 1.1 3 LVPECL + 4 CMOS (DIV ON) 1.0 4 LVPECL ONLY (DIV ON) 0.2 05046-060 0 0 400 OUTPUT FREQUENCY (MHz) 800 05046-061 0.9 0.1 0.8 0 Figure 7. Power vs. Frequency—LVPECL, LVDS (PLL Off) 20 CLK1 (EVAL BOARD) 3GHz 40 60 80 OUTPUT FREQUENCY (MHz) 100 120 Figure 10. Power vs.
PAGE 21
AD9510 10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 05046-058 10 –80 –90 CENTER 245.75MHz 30kHz/ –80 –90 CENTER 61.44MHz SPAN 300kHz 30kHz/ SPAN 300kHz Figure 15. Phase Noise, LVPECL, DIV 4, fVCXO = 245.76 MHz, fOUT = 61.44 MHz, fPFD = 1.2288 MHz, R = 25, N = 200 Figure 12. Phase Noise, LVPECL, DIV 1, FVCXO = 245.76 MHz, fOUT = 245.76 MHz, fPFD = 1.2288 MHz, R = 25, N = 200 –135 –20 –30 –40 –50 –60 –70 05046-063 –80 100 CENTER 1.
PAGE 22
AD9510 Data Sheet 1.8 DIFFERENTIAL SWING (V p-p) 1.7 1.6 1.5 1.4 VERT 500mV/DIV 05046-056 05046-053 1.3 1.2 100 HORIZ 500ps/DIV 600 1100 1600 OUTPUT FREQUENCY (MHz) Figure 21. LVPECL Differential Output Swing vs. Frequency Figure 18. LVPECL Differential Output at 800 MHz VERT 100mV/DIV 700 650 600 550 500 100 HORIZ 500ps/DIV 05046-050 05046-054 DIFFERENTIAL SWING (mV p-p) 750 300 500 700 OUTPUT FREQUENCY (MHz) 900 Figure 22. LVDS Differential Output Swing vs.
PAGE 23
–110 –120 –120 –130 –130 –140 –150 –160 –160 05046-051 –150 100 1k 100k 10k OFFSET (Hz) –170 10 10M 1M 100 1k 10k 100k OFFSET (Hz) 10M 1M Figure 27. Additive Phase Noise—LVPECL DIV1, 622.08 MHz –80 –80 –90 –90 –100 –100 –110 –110 –120 –130 –120 –130 –140 –140 –150 –150 100 1k 10k 100k OFFSET (Hz) 1M –160 –170 10 10M Figure 25. Additive Phase Noise—LVDS DIV 1, 245.
PAGE 24
AD9510 Data Sheet TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave has a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.
PAGE 25
Data Sheet AD9510 TYPICAL MODES OF OPERATION PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY CLOCK DISTRIBUTION CLOCK DISTRIBUTION ONLY This is the most common operational mode for the AD9510. An external oscillator (shown as VCO/VCXO) is phase locked to a reference input frequency applied to REFIN. The loop filter is usually a passive design. A VCO or a VCXO can be used. The CLK2 input is connected internally to the feedback divider, N. The CLK2 input provides the feedback path for the PLL.
PAGE 26
AD9510 Data Sheet PLL WITH EXTERNAL VCO AND BAND-PASS FILTER FOLLOWED BY CLOCK DISTRIBUTION An external band-pass filter (BPF) can be used to improve the phase noise and spurious characteristics of the PLL output. This option is most appropriate to optimize cost by choosing a less expensive VCO combined with a moderately priced filter. Note that the BPF is shown outside of the VCO-to-N divider path, with the BP filter outputs routed to CLK1.
PAGE 27
Data Sheet AD9510 VS GND RSET DISTRIBUTION REF REFIN R DIVIDER REFINB N DIVIDER FUNCTION AD9510 PHASE FREQUENCY DETECTOR SYNCB, RESETB, PDB PLL REF CHARGE PUMP PLL SETTINGS CLK1 1.6GHz CP STATUS CLK2 CLK1B CLK2B PROGRAMMABLE DIVIDERS AND PHASE ADJUST 1.6GHz LVPECL OUT0 /1, /2, /3... /31, /32 OUT0B LVPECL OUT1 /1, /2, /3... /31, /32 OUT1B 1.2GHz LVPECL LVPECL OUT2 /1, /2, /3... /31, /32 OUT2B SCLK SDIO SDO LVPECL SERIAL CONTROL PORT OUT3 /1, /2, /3...
PAGE 28
AD9510 Data Sheet FUNCTIONAL DESCRIPTION OVERALL PLL Reference Input—REFIN Figure 33 shows a block diagram of the AD9510. The chip combines a programmable PLL core with a configurable clock distribution system. A complete PLL requires the addition of a suitable external VCO (or VCXO) and loop filter. This PLL can lock to a reference input signal and produce an output that is related to the input frequency by the ratio defined by the programmable R and N dividers.
PAGE 29
Data Sheet AD9510 VCO/VCXO Feedback Divider—N (P, A, B) A and B Counters The N divider is a combination of a prescaler, P (3 bits), and two counters, A (6 bits) and B (13 bits). Although the PLL of the AD9510 is similar to the ADF4106, the AD9510 has a redesigned prescaler that allows lower values of N. The prescaler has both a dual modulus (DM) and a fixed divide (FD) mode. The AD9510 prescaler modes are shown in Table 15.
PAGE 30
AD9510 Data Sheet Phase Frequency Detector (PFD) and Charge Pump eliminates the dead zone around the phase-locked condition and thereby reduces the potential for certain spurs that can be impressed on the VCO signal. The PFD takes inputs from the R counter and the N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 36 is a simplified schematic.
PAGE 31
Data Sheet AD9510 An analog lock detect (ALD) signal can be selected. When ALD is selected, the signal at the STATUS pin is either an open-drain P-channel (Register 0x08[5:2] = 1100) or an open-drain N-channel (Register 0x08[5:2] = 0101b). The analog lock detect signal is true (relative to the selected mode) with brief false pulses. These false pulses shorten as the inputs to the PFD are nearer to coincidence and longer as they are further from coincidence.
PAGE 32
AD9510 Data Sheet FUNCTION PIN DISTRIBUTION SECTION The FUNCTION pin (16) has three functions that are selected by the value in Register 0x58[6:5]. This pin is internally pulled down by a 30 kΩ resistor. If this pin is left unconnected, the part is in reset by default. To avoid this, connect this pin to VS with a 1 kΩ resistor. As previously mentioned, the AD9510 is partitioned into two operational sections: PLL and distribution. The PLL Section is discussed previously in this data sheet.
PAGE 33
Data Sheet AD9510 Example 1: Although the second set of settings produces the same divide ratio, the resulting duty cycle is not the same. Set the Divide Ratio = 2 Setting the Duty Cycle HIGH_CYCLES = 0 Example 2: The duty cycle and the divide ratio are related. Different divide ratios have different duty cycle options. For example, if Divide Ratio = 2, the only duty cycle possible is 50%. If the Divide Ratio = 4, the duty cycle can be 25%, 50%, or 75%.
PAGE 34
AD9510 Data Sheet Address 0x48 to Address 0x56 Divide Ratio 12 12 12 12 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 Duty Cycle (%) 83 17 92 8 54 46 62 38 69 31 77 23 85 15 92 8 50 57 43 64 36 71 29 79 21 86 14 93 7 53 47 60 40 67 33 73 27 80 20 87 13 93 7 50 56 44 63 38 69 31 LO[7:4] 1 9 0 A 5 6 4 7 3 8 2 9 1 A 0 B 6 5 7 4 8 3 9 2 A 1 B 0 C 6 7 5 8 4 9 3 A 2 B 1 C 0 D 7 6 8 5 9 4 A HI[3:0] 9 1 A 0 6 5 7 4 8 3
PAGE 35
Data Sheet AD9510 Address 0x48 to Address 0x56 Divide Ratio 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 21 21 21 21 21 21 21 21 21 21 21 21 22 22 22 22 22 22 22 22 22 22 22 23 23 23 23 23 23 23 23 23 Duty Cycle (%) 21 84 16 50 55 45 60 40 65 35 70 30 75 25 80 20 52 48 57 43 62 38 67 33 71 29 76 24 50 55 45 59 41 64 36 68 32 73 27 52 48 57 43 61 39 65 35 70 LO[7:4] E 2 F 9 8 A 7 B 6 C 5 D 4 E 3 F 9 A 8 B 7 C 6 D 5 E 4 F A 9 B 8 C 7 D 6 E 5 F A B 9 C 8 D 7 E 6 HI[3:0] 3 F 2 9 A 8 B 7 C 6 D 5 E 4 F 3
PAGE 36
AD9510 Data Sheet Divider Phase Offset Table 19. Phase Offset—Start H/L Bit The phase of each output can be selected, depending on the divide ratio chosen. This is selected by writing the appropriate values to the registers which set the phase and start high/low bit for each output. These are the odd numbered registers from Register 0x49 to Register 0x57. Each divider has a 4-bit phase offset [3:0] and a start high or low bit [4].
PAGE 37
Data Sheet AD9510 Phase offsets can be related to degrees by calculating the phase step for a particular divide ratio: Phase Step = 360°/(Divide Ratio) = 360°/DIV Calculating the Delay The following values and equations are used to calculate the delay of the delay block. Value of Ramp Current Control Bits (Register 0x35 or Register 0x39 [2:0]) = IRAMP_BITS Using some of the same examples, DIV = 4 IRAMP (µA) = 200 × (IRAMP_BITS + 1) Phase Step = 360°/4 = 90° No. of Caps = No.
PAGE 38
AD9510 Data Sheet POWER-DOWN MODES Chip Power-Down or Sleep Mode—PDB The PDB chip power-down turns off most of the functions and currents in the AD9510. When the PDB mode is enabled, a chip power-down is activated by taking the FUNCTION pin to a logic low level. The chip remains in this power-down state until PDB is brought back to logic high.
PAGE 39
Data Sheet AD9510 SYNCB—Hardware SYNC The AD9510 clocks can be synchronized to each other at any time. The outputs of the clocks are forced into a known state with respect to each other and then allowed to continue clocking from that state in synchronicity. Before a synchronization is done, the FUNCTION Pin must be set to act as the SYNCB: Register 0x58[6:5] = 01b input (Register 0x58[6:5] = 01b). Synchronization is done by forcing the FUNCTION pin low, creating a SYNCB signal and then releasing it.
PAGE 40
AD9510 Data Sheet SERIAL CONTROL PORT The AD9510 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9510 serial control port is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR® protocols. The serial control port allows read/write access to all registers that configure the AD9510.
PAGE 41
Data Sheet AD9510 Read If the instruction word is for a read operation (I15 = 1b), the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 4 as determined by W1:W0. The readback data is valid on the falling edge of SCLK. The default mode of the AD9510 serial control port is unidirectional mode; therefore, the requested data appears on the SDO pin.
PAGE 42
AD9510 Data Sheet Table 22.
PAGE 43
Data Sheet AD9510 tH tS CSB tCLK tLO tHI tDS SCLK SDIO BI N 05046-040 tDH BI N + 1 Figure 51. Serial Control Port Timing—Write Table 23.
PAGE 44
AD9510 Data Sheet REGISTER MAP AND DESCRIPTION SUMMARY TABLE Table 24. AD9510 Register Map Addr (Hex) 00 Parameter Serial control port configuration Bit 7 (MSB) SDO inactive (bidirectional mode) Bit 6 LSB_ FIRST Bit 5 Soft reset 01 02 03 Bit 4 Long instruction Bit 3 Bit 2 Bit 1 Not used Bit 0 (LSB) Def.
PAGE 45
Data Sheet Addr (Hex) 3E 3F 40 Parameter LVPECL OUT2 LVPECL OUT3 LVDS_CMOS OUT4 AD9510 Bit 7 (MSB) Bit 6 Bit 5 Not used Not used Not used 41 LVDS_CMOS OUT5 Not used 42 LVDS_CMOS OUT6 Not used 43 LVDS_CMOS OUT7 Not used 44 45 CLK1 and CLK2 Clocks select, power-down (PD) options Not used CLKs in PD 55 56 57 58 59 5A CMOS inverted driver on CMOS inverted driver on CMOS inverted driver on CMOS inverted driver on Not used REFIN PD Def.
PAGE 46
AD9510 Data Sheet REGISTER MAP DESCRIPTION Table 25 lists the AD9510 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by square brackets. For example, [3] refers to Bit 3, while [5:2] refers to the range of bits from Bit 5 through Bit 2. Table 25 describes the functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 24. Table 25. AD9510 Register Descriptions Reg. Addr.
PAGE 47
Data Sheet Reg. Addr.
PAGE 48
AD9510 Data Sheet Reg. Addr. (Hex) Bit(s) Name 0A [4:2] Prescaler value (P/P + 1) 0A 0A [5] [6] 0A 0B [7] [5:0] 0C [7:0] 0D [1:0] 0D 0D [4:2] [5] 0D 0D [6] [7] 0E33 [0] 34 38 34 38 [7:1] B counter bypass Description [4] [3] [2] Mode Prescaler Mode 0 0 0 FD Divide by 1 0 0 1 FD Divide by 2 0 1 0 DM 2/3 0 1 1 DM 4/5 1 0 0 DM 8/9 1 0 1 DM 16/17 1 1 0 DM 32/33 1 1 1 FD Divide by 3 DM = dual modulus, FD = fixed divide. Not used.
PAGE 49
Data Sheet Reg. Addr. (Hex) Bit(s) [2:0] 35 39 [5:3] 35 39 Name Ramp current OUT5 OUT6 Ramp capacitor OUT5 OUT6 AD9510 Description The slowest ramp (200 µA) sets the longest full scale of approximately 10 ns. [2] [1] [0] 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Selects the number of capacitors in ramp generation circuit. More capacitors → slower ramp.
PAGE 50
AD9510 Data Sheet Reg. Addr. (Hex) Bit(s) Name 3C [7:4] 3D 3E 3F 40 [0] Power-down 41 LVDS/CMOS 42 OUT4 43 OUT5 OUT6 OUT7 40 [2:1] Output current level 41 LVDS 42 OUT4 43 OUT5 OUT6 OUT7 40 41 42 43 [3] [4] 40 41 42 43 40 41 42 43 44 45 45 45 45 [7:0] [0] [1] [2] [3] 45 45 [4] [5] 45 46 47 [7:6] [7:0] [7:0] [7:5] Description Not used. Power-down bit for both output and LVDS driver. 0 = LVDS/CMOS on (default), 1 = LVDS/CMOS power-down. [2] [1] Current (mA) 0 0 1.75 0 1 3.5 (default) 1 0 5.
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Data Sheet Reg. Addr. (Hex) Bit(s) [3:0] 48 4A 4C 4E 50 52 54 56 [7:4] 48 4A 4C 4E 50 52 54 56 [3:0] 49 4B 4D 4F 51 53 55 57 [4] 49 4B 4D 4F 51 53 55 57 [5] Name Divider high OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 Divider low OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 Phase offset OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 Start OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 Force 49 4B 4D 4F 51 53 55 57 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 AD9510 Description Number of clock cycles divider output stays high.
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AD9510 Data Sheet Reg. Addr. (Hex) Bit(s) [6] 49 4B 4D 4F 51 53 55 57 [7] 49 4B 4D 4F 51 53 55 57 58 [0] Name Nosync OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 Bypass divider OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 SYNC detect enable 58 [1] SYNC select 58 [2] Soft SYNC 58 [3] 58 [4] Dist ref power-down SYNC power-down 1 = power down the SYNC (default = 0b). 58 [6:5] 58 59 5A [7] [7:0] [0] 5A End [7:1] Description Ignore chip-level sync signal (default = 0b).
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Data Sheet AD9510 POWER SUPPLY The AD9510 requires a 3.3 V ± 5% power supply for VS. The tables in the Specifications section give the performance expected from the AD9510 with the power supply voltage within this range. The absolute maximum range of −0.3 V − +3.6 V, with respect to GND, must never be exceeded on the VS pin. Follow good engineering practice in the layout of power supply traces and the ground plane of the printed circuit board (PCB).
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AD9510 Data Sheet APPLICATIONS INFORMATION USING THE AD9510 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer; any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-todigital output.
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Data Sheet AD9510 Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9510 offers both LVPECL and LVDS outputs, which are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
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AD9510 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 MAX 0.60 MAX 64 49 48 PIN 1 INDICATOR 1 PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.30 0.23 0.18 0.25 MIN 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION 06-13-2012-A 0.05 MAX 0.02 NOM SEATING PLANE 16 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 4.