Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9511BCPZ

1.2 GHz Clock Distribution IC, PLL Core,

Dividers, Delay Adjust, Five Outputs

AD9511

Rev. A

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FEATURES

Low phase noise phase-locked loop core

Reference input frequencies to 250 MHz

Programmable dual-modulus prescaler

Programmable charge pump (CP) current

Separate CP supply (VCP

) extends tuning range

Two 1.6 GHz, differential clock inputs

5 programmable dividers, 1 to 32, all integers

Phase select for output-to-output coarse delay adjust

3 independent 1.2 GHz LVPECL outputs

Additive output jitter 225 fs rms

2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter 275 fs rms

Fine delay adjust on 1 LVDS/CMOS output

Serial control port

Space-saving 48-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

FUNCTIONAL BLOCK DIAGRAM

05286-001

R DIVIDER

N DIVIDER

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

PLL

SETTINGS

CLK2

STATUS

CLK2B

PROGRAMMABLE

DIVIDERS AND

PHASE ADJUST

OUT0

OUT0B

LVPECL

/1, /2, /3... /31, /32

OUT1

OUT1B

LVPECL

/1, /2, /3... /31, /32

OUT2

OUT2B

LVPECL

/1, /2, /3... /31, /32

OUT3

OUT3B

LVDS/CMOS

/1, /2, /3... /31, /32

OUT4

OUT4B

LVDS/CMOS

/1, /2, /3... /31, /32

DELAY

ADJUST

CLK1

CLK1B

REFIN

REFINB

FUNCTION

SCLK

SDIO

SDO

CSB

SERIAL

CONTROL

PORT

CPRSE

DISTRIBUTION

REF

SYNCB,

RESETB

PDB

RSE

AD9511

GND

PLL

REF

Figure 1.

GENERAL DESCRIPTION

The AD9511 provides a multi-output clock distribution

function along with an on-chip PLL core. The design

emphasizes low jitter and phase noise to maximize data

converter performance. Other applications with demanding

phase noise and jitter requirements also benefit from this part.

The PLL section consists of a programmable reference divider

(R); a low noise phase frequency detector (PFD); a precision

charge pump (CP); and a programmable feedback divider (N).

By connecting an external VCXO or VCO to the CLK2/CLK2B

pins, frequencies up to 1.6 GHz may be synchronized to the

input reference.

There are five independent clock outputs. Three outputs are

LVPECL (1.2 GHz), and two are selectable as either LVDS

(800 MHz) or CMOS (250 MHz) levels.

Each output has a programmable divider that may be bypassed

or set to divide by any integer up to 32. The phase of one clock

output relative to another clock output may be varied by means

of a divider phase select function that serves as a coarse timing

adjustment. One of the LVDS/CMOS outputs features a

programmable delay element with full-scale ranges up to 10 ns

of delay. This fine tuning delay block has 5-bit resolution, giving

32 possible delays from which to choose for each full-scale

setting.

The AD9511 is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9511 is available in a 48-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated by

connecting the charge pump supply (VCP) to 5.5 V. The

temperature range is −40°C to +85°C.

Summary of content (60 pages)

PAGE 1
.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs AD9511 FEATURES FUNCTIONAL BLOCK DIAGRAM VS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core.
PAGE 2
AD9511 TABLE OF CONTENTS Specifications..................................................................................... 4 A and B Counters................................................................... 30 PLL Characteristics ...................................................................... 4 Determining Values for P, A, B, and R ................................ 30 Clock Inputs ..................................................................................
PAGE 3
AD9511 Single-Chip Synchronization.....................................................40 Summary Table............................................................................45 SYNCB—Hardware SYNC ....................................................40 Register Map Description ..........................................................47 Soft SYNC—Register 58h<2> ...............................................40 Power Supply ...........................................................................
PAGE 4
AD9511 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCPS ≤ 5.5 V, TA = 25°C, RSET = 4.12 kΩ, CPRSET = 5.1 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. PLL CHARACTERISTICS Table 1.
PAGE 5
AD9511 Parameter NOISE CHARACTERISTICS In-Band Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) Min Typ Max Unit Test Conditions/Comments The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
PAGE 6
AD9511 CLOCK OUTPUTS Table 3. Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2; Differential Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Output Differential Voltage (VOD) LVDS CLOCK OUTPUTS OUT3, OUT4; Differential Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) CMOS CLOCK OUTPUTS OUT3, OUT4 Output Frequency Output Voltage High (VOH) Output Voltage Low (VOL) Min Typ Max Unit VS − 1.22 VS − 2.
PAGE 7
AD9511 TIMING CHARACTERISTICS Table 4.
PAGE 8
AD9511 Parameter DELAY ADJUST Shortest Delay Range 4 Zero Scale Full Scale Linearity, DNL Linearity, INL Longest Delay Range4 Zero Scale Full Scale Linearity, DNL Linearity, INL Delay Variation with Temperature Long Delay Range, 10 ns 5 Zero Scale Full Scale Short Delay Range, 1 ns5 Zero Scale Full Scale Min Typ Max Unit 0.05 0.72 0.36 1.12 0.5 0.8 0.68 1.51 ns ns LSB LSB 0.20 9.0 0.57 10.2 0.3 0.6 0.95 11.6 ns ns LSB LSB 0.35 −0.14 ps/°C ps/°C 0.51 0.
PAGE 9
AD9511 CLOCK OUTPUT PHASE NOISE Table 5. Parameter CLK1-TO-LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 38.
PAGE 10
AD9511 Parameter CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT= 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 491.52 MHz, OUT = 245.
PAGE 11
AD9511 Parameter @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1-TO-CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset > 10 MHz Offset CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUT = 78.
PAGE 12
AD9511 CLOCK OUTPUT ADDITIVE TIME JITTER Table 6. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 155.
PAGE 13
AD9511 Parameter CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 LVDS (OUT4) = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 LVDS (OUT3) = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs Off) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs Off) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outpu
PAGE 14
AD9511 Parameter CLK1 = 400 MHz Min CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz CMOS (OUT4) = 50 MHz (B Output On) DELAY BLOCK ADDITIVE TIME JITTER 1 100 MHz Output Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000 Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111 Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000 Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111 Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000 Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111 Delay FS = 4 ns (400 μA, 4C) Fine Adj.
PAGE 15
AD9511 SERIAL CONTROL PORT Table 8.
PAGE 16
AD9511 STATUS PIN Table 10. Parameter OUTPUT CHARACTERISTICS Min Output Voltage High (VOH) Output Voltage Low (VOL) MAXIMUM TOGGLE RATE 2.7 ANALOG LOCK DETECT Capacitance Typ Max Unit 0.4 100 V V MHz 3 pF Test Conditions/Comments When selected as a digital output (CMOS); there are other modes in which the STATUS pin is not CMOS digital output. See Figure 37. Applies when PLL mux is set to any divider or counter output, or PFD up/down pulse. Also applies in analog lock detect mode.
PAGE 17
AD9511 TIMING DIAGRAMS tCLK1 CLK1 DIFFERENTIAL tPECL 80% LVDS tLVDS tCMOS tRL tFL 05286-065 05286-002 20% Figure 4. LVDS Timing, Differential Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode SINGLE-ENDED DIFFERENTIAL 80% 80% CMOS 3pF LOAD LVPECL tFP 05286-064 tRP tRC tFC Figure 5. CMOS Timing, Single-Ended, 3 pF Load Figure 3. LVPECL Timing, Differential Rev.
PAGE 18
AD9511 ABSOLUTE MAXIMUM RATINGS Table 12. Parameter or Pin VS VCP VCP REFIN, REFINB RSET CPRSET CLK1, CLK1B, CLK2, CLK2B CLK1 CLK2 SCLK, SDIO, SDO, CSB OUT0, OUT1, OUT2, OUT3, OUT4 FUNCTION STATUS Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to GND GND VS GND GND GND GND CLK1B CLK2B GND GND Min −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −1.2 −1.2 −0.3 −0.3 Max +3.6 +5.8 +5.8 VS + 0.3 VS + 0.3 VS + 0.3 VS + 0.3 +1.2 +1.2 VS + 0.3 VS + 0.
PAGE 19
AD9511 48 47 46 45 44 43 42 41 40 39 38 37 VS CPRSET GND RSET VS GND OUT0 OUT0B VS VS GND GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AD9511 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 VS OUT3 OUT3B VS VS OUT4 OUT4B VS VS OUT1 OUT1B VS 05286-003 STATUS SCLK SDIO SDO CSB VS GND OUT2B OUT2 VS VS GND 13 14 15 16 17 18 19 20 21 22 23 24 REFIN 1 REFINB 2 VS 3 VCP 4 CP 5 VS 6 CLK2 7 CLK2B 8 VS 9 CLK1 10 CLK1B 11 FUNCTION 12 Figure 6.
PAGE 20
AD9511 Table 13. Pin Function Descriptions Pin No. 1 2 3, 6, 9, 18, 22, 23, 25, 28, 29, 32, 33, 36, 39, 40, 44, 48 4 Mnemonic REFIN REFINB VS Description PLL Reference Input. Complementary PLL Reference Input. Power Supply (3.3 V). VCP 5 7 CP CLK2 8 10 11 12 CLK2B CLK1 CLK1B FUNCTION 13 14 15 16 17 19, 24, 37, 38, 43, 46 20 21 26 27 30 31 34 35 41 42 45 47 STATUS SCLK SDIO SDO CSB GND Charge Pump Power Supply. It should be greater than or equal to VS. VCP can be set as high as 5.
PAGE 21
AD9511 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 degrees to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.
PAGE 22
AD9511 TYPICAL PERFORMANCE CHARACTERISTICS 0.6 0.7 DEFAULT – 3 LVPECL + 2 LVDS (DIV ON) POWER (W) 0.6 POWER (W) 0.5 3 LVPECL + 2 LVDS (DIV BYPASSED) 0.4 3 LVPECL + 2 CMOS (DIV ON) 0.5 0.3 0 400 OUTPUT FREQUENCY (MHz) 800 Figure 7. Power vs. Frequency—LVPECL, LVDS (PLL Off) 05286-081 2 LVDS (DIV ON) 05286-080 3 LVPECL (DIV ON) 0.4 0 20 100 120 Figure 10. Power vs.
PAGE 23
10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 05286-058 10 –80 –90 CENTER 245.75MHz 30kHz/ –80 –90 CENTER 61.44MHz SPAN 300kHz 30kHz/ SPAN 300kHz Figure 15. Phase Noise, LVPECL, DIV 4, FVCXO = 245.76 MHz, FOUT = 61.44 MHz, FPFD = 1.2288 MHz, R = 25, N = 200 Figure 12. Phase Noise, LVPECL, DIV 1, FVCXO = 245.76 MHz, FOUT = 245.76 MHz, FPFD = 1.2288 MHz, R = 25, N = 200 –20 –30 –40 –50 –60 –70 05286-063 –80 –90 100 250kHz/ –145 –150 –155 –160 –165 –170 0.
PAGE 24
AD9511 DIFFERENTIAL SWING (V p-p) 1.8 1.7 1.6 1.5 1.4 VERT 500mV/DIV 05286-056 05286-053 1.3 1.2 100 HORIZ 500ps/DIV 600 1100 1600 OUTPUT FREQUENCY (MHz) Figure 18. LVPECL Differential Output @ 800 MHz Figure 21. LVPECL Differential Output Swing vs. Frequency VERT 100mV/DIV 700 650 600 550 500 100 HORIZ 500ps/DIV 05286-050 05286-054 DIFFERENTIAL SWING (mV p-p) 750 300 500 700 900 OUTPUT FREQUENCY (MHz) Figure 19. LVDS Differential Output @ 800 MHz Figure 22.
PAGE 25
–110 –120 –120 –130 –130 –140 –140 –150 –150 –160 –160 1k 10k 100k OFFSET (Hz) 1M –170 10 10M –80 –90 –90 –100 –100 –110 –110 L(f) (dBc/Hz) –80 –120 –130 –150 –150 –160 1k 10k 100k OFFSET (Hz) 1M –170 10 10M –110 –120 –120 L(f) (dBc/Hz) –110 –130 –140 –160 –160 1M 10k 100k OFFSET (Hz) 1M 10M –140 –150 10k 100k OFFSET (Hz) 1k –130 –150 05286-045 L(f) (dBc/Hz) –100 1k 100 Figure 28. Additive Phase Noise—LVDS DIV2, 122.
PAGE 26
AD9511 TYPICAL MODES OF OPERATION CLOCK DISTRIBUTION ONLY PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY CLOCK DISTRIBUTION This is the most common operational mode for the AD9511. An external oscillator (shown as VCO/VCXO) is phase locked to a reference input frequency applied to REFIN. The loop filter is usually a passive design. A VCO or a VCXO can be used. The CLK2 input is connected internally to the feedback divider, N. The CLK2 input provides the feedback path for the PLL.
PAGE 27
AD9511 PLL WITH EXTERNAL VCO AND BAND-PASS FILTER FOLLOWED BY CLOCK DISTRIBUTION An external band-pass filter may be used to try to improve the phase noise and spurious characteristics of the PLL output. This option is most appropriate to optimize cost by choosing a less expensive VCO combined with a moderately priced filter. Note that the BPF is shown outside of the VCO-to-N divider path, with the BP filter outputs routed to CLK1.
PAGE 28
AD9511 VS RSET GND DISTRIBUTION REF REFIN R DIVIDER REFINB N DIVIDER FUNCTION 1.6GHz AD9511 PHASE FREQUENCY DETECTOR SYNCB, RESETB PDB PLL REF CHARGE PUMP PLL SETTINGS CLK1 CP STATUS CLK2 CLK1B 1.6GHz CLK2B PROGRAMMABLE DIVIDERS AND PHASE ADJUST LVPECL OUT0 /1, /2, /3... /31, /32 OUT0B LVPECL OUT1 /1, /2, /3... /31, /32 OUT1B 1.2GHz LVPECL LVPECL OUT2 /1, /2, /3... /31, /32 OUT2B SCLK SDIO SDO LVDS/CMOS SERIAL CONTROL PORT OUT3 /1, /2, /3...
PAGE 29
AD9511 FUNCTIONAL DESCRIPTION Figure 33 shows a block diagram of the AD9511. The chip combines a programmable PLL core with a configurable clock distribution system. A complete PLL requires the addition of a suitable external VCO (or VCXO) and loop filter. This PLL can lock to a reference input signal and produce an output that is related to the input frequency by the ratio defined by the programmable R and N dividers.
PAGE 30
AD9511 Table 14. PLL Prescaler Modes Mode (FD = Fixed Divide DM = Dual Modulus) FD FD P = 2 DM P = 4 DM P = 8 DM P = 16 DM P = 32 DM FD A and B Counters Value in 0Ah<4:2> 000 001 010 011 100 101 110 111 Divide By 1 2 P/P + 1 = 2/3 P/P + 1 = 4/5 P/P + 1 = 8/9 P/P + 1 = 16/17 P/P + 1 = 32/33 3 When using the prescaler in FD mode, the A counter is not used, and the B counter may need to be bypassed. The DM prescaler modes set some upper limits on the frequency, which can be applied to CLK2. See Table 15.
PAGE 31
AD9511 Phase Frequency Detector (PFD) and Charge Pump Antibacklash Pulse The PFD takes inputs from the R counter and the N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 36 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs.
PAGE 32
AD9511 An analog lock detect (ALD) signal may be selected. When ALD is selected, the signal at the STATUS pin is either an opendrain P-channel (08h<5:2> = 1100b) or an open-drain Nchannel (08h<5:2> = 0101b). The analog lock detect signal is true (relative to the selected mode) with brief false pulses. These false pulses get shorter as the inputs to the PFD are nearer to coincidence and longer as they are further from coincidence.
PAGE 33
AD9511 Each divider can be configured for divide ratio, phase, and duty cycle. The phase and duty cycle values that can be selected depend on the divide ratio that is chosen. or power-down. When the SYNCB function is selected, the FUNCTION pin does not act as either RESETB or PDB. PDB: 58h<6:5> = 11b The FUNCTION pin may also be programmed to work as an asynchronous full power-down, PDB.
PAGE 34
AD9511 Table 17.
PAGE 35
AD9511 Divide Ratio 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 Duty Cycle (%) 20 87 13 93 7 50 56 44 63 38 69 31 75 25 81 19 88 13 94 6 53 47 59 41 65 35 71 29 76 24 82 18 88 12 94 6 50 56 44 61 39 67 33 72 28 78 22 83 17 89 11 4Ah to 52h LO<7:4> HI<3:0> B 1 C 0 D 7 6 8 5 9 4 A 3 B 2 C 1 D 0 E 7 8 6 9 5 A 4 B 3 C 2 D 1 E 0 F 8 7 9 6 A 5 B 4 C 3 D 2 E 1 F 2 C 1 D 0 7 8 6 9 5 A 4 B 3 C 2 D 1 E 0 8
PAGE 36
AD9511 Divide Ratio 23 23 23 23 23 23 23 23 23 24 24 24 24 24 24 24 24 24 25 25 25 25 25 25 25 25 26 26 Duty Cycle (%) 48 57 43 61 39 65 35 70 30 50 54 46 58 42 63 38 67 33 52 48 56 44 60 40 64 36 50 54 4Ah to 52h LO<7:4> HI<3:0> B 9 C 8 D 7 E 6 F B A C 9 D 8 E 7 F B C A D 9 E 8 F C B A C 9 D 8 E 7 F 6 B C A D 9 E 8 F 7 C B D A E 9 F 8 C D Divide Ratio 26 26 26 26 26 27 27 27 27 27 27 28 28 28 28 28 29 29 29 29 30 30 30 31 31 32 Rev.
PAGE 37
AD9511 In general, by combining the 4-bit phase offset and the Start H/L bit, there are 32 possible phase offset states (see Table 18). Divider Phase Offset The phase of each output may be selected, depending on the divide ratio chosen. This is selected by writing the appropriate values to the registers, which set the phase and start high/low bit for each output. These are the odd numbered registers from 4Bh to 53h. Each divider has a 4-bit phase offset <3:0> and a start high or low bit <4>. Table 18.
PAGE 38
AD9511 DIV = 18 Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 Phase offsets may be related to degrees by calculating the phase step for a particular divide ratio: Phase Step = 360°/(Divide Ratio) = 360°/DIV This path adds some jitter greater than that specified for the nondelay outputs. This means that the delay function should be used primarily for clocking digital chips, such as FPGA, ASIC, DUC, and DDC, rather than for data converters.
PAGE 39
AD9511 Table 19. Register 0Ah: PLL Power-Down 3.5mA <1> 0 0 1 1 OUT OUTB In synchronous power-down mode, the PLL power-down is gated by the charge pump to prevent unwanted frequency jumps. The device goes into power-down on the occurrence of the next charge pump event after the registers are updated. Figure 42. LVDS Output Simplified Equivalent Circuit POWER-DOWN MODES Chip Power-Down or Sleep Mode—PDB The PDB chip power-down turns off most of the functions and currents in the AD9511.
PAGE 40
AD9511 The AD9511 has several ways to force the chip into a reset condition. Power-On Reset—Start-Up Conditions when VS is Applied A power-on reset (POR) is issued when the VS power supply is turned on. This initializes the chip to the power-on conditions that are determined by the default register settings. These are indicated in the default value column of Table 23.
PAGE 41
AD9511 SERIAL CONTROL PORT The AD9511 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9511 serial control port is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The serial control port allows read/write access to all registers that configure the AD9511.
PAGE 42
AD9511 writing to Register 5Ah<0> = 1b. This update bit is self-clearing (it is not required to write 0 to it to clear it). Since any number of bytes of data can be changed before issuing an update command, the update simultaneously enables all register changes since any previous update. Phase offsets or divider synchronization is not effective until a SYNC is issued (see the Single-Chip Synchronization section).
PAGE 43
AD9511 Table 21. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 = 0 A8 = 0 A7 = 0 A6 A5 A4 A3 A2 A1 A0 CSB SCLK DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16-BIT INSTRUCTION HEADER D7 D6 D5 D4 D3 D2 D1 D0 D7 REGISTER (N) DATA D6 D5 D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 05286-019 SDIO DON'T CARE DON'T CARE Figure 46.
PAGE 44
AD9511 tS tH CSB tCLK tHI tLO tDS SCLK SDIO BI N 05286-040 tDH BI N + 1 Figure 51. Serial Control Port Timing—Write Table 22.
PAGE 45
AD9511 REGISTER MAP AND DESCRIPTION SUMMARY TABLE Table 23. AD9511 Register Map Addr (Hex) 00 Parameter Serial Control Port Configuration Bit 7 (MSB) SDO Inactive (Bidirectional Mode) Bit 6 LSB First Bit 5 Soft Reset Bit 4 Long Instruction Bit 3 Bit 2 Bit 1 Not Used Bit 0 (LSB) Def.
PAGE 46
AD9511 Addr (Hex) 3D Parameter OUTPUTS LVPECL OUT0 Bit 7 (MSB) Bit 6 Bit 5 3E LVPECL OUT1 Not Used 3F LVPECL OUT2 Not Used 40 LVDS_CMOS OUT 3 Not Used 41 LVDS_CMOS OUT 4 Not Used Not Used 45 Not Used CLKs in PD 4A 4B DIVIDERS Divider 0 Divider 0 Bypass 4C 4D Divider 1 Divider 1 Bypass 4E 4F Divider 2 Divider 2 Bypass 50 51 Divider 3 Divider 3 Bypass 52 53 Divider 4 Divider 4 Bypass Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Syn
PAGE 47
AD9511 REGISTER MAP DESCRIPTION Table 24 lists the AD9511 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 24 describes the functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 23. Table 24. AD9511 Register Descriptions Reg. Addr.
PAGE 48
AD9511 Reg. Addr.
PAGE 49
AD9511 Reg. Addr. (Hex) 0A 0A Bit(s) Name <1:0> PLL Power-Down <0> 0 1 0 1 Mode Normal Operation Asynchronous Power-Down Normal Operation Synchronous Power-Down <4:2> Prescaler Value (P/P+1) 0A 0A <5> <6> 0A 0B <7> <5:0> 0C <7:0> 0D <1:0> 0D 0D <4:2> <5> 0D <6> 0D <7> 0E-33 Description 01 = Asynchronous Power-Down (Default).
PAGE 50
AD9511 Reg. Addr. (Hex) 34 34 35 35 35 36 36 Bit(s) Name Fine Delay Adjust <0> Delay Control OUT4 <7:1> <2:0> Ramp Current OUT4 Description Delay Block Control Bit. Bypasses Delay Block and Powers It Down (Default = 1b). Not Used. The slowest ramp (200 μs) sets the longest full scale of approximately 10 ns. <2> <1> <0> 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 <5:3> Ramp Capacitor Selects the Number of Capacitors in Ramp Generation Circuit. OUT4 More Capacitors => Slower Ramp.
PAGE 51
AD9511 Reg. Addr. (Hex) Bit(s) Name 3D (3E) (3F) <3:2> Output Level LVPECL OUT0 (OUT1) (OUT2) 3D (3E) (3F) <7:4> 40 (41) <0> Power-Down LVDS/CMOS OUT3 (OUT4) 40 (41) <2:1> Output Current Level LVDS OUT3 (OUT4) 40 (41) <3> 40 (41) <4> LVDS/CMOS Select OUT3 (OUT4) Inverted CMOS Driver OUT3 (OUT4) 40 (41) <7:5> 42 (43) (44) <7:0> 45 45 45 45 45 45 45 46 (47) (48) (49) <0> Description Output Single-Ended Voltage Levels for LVPECL Outputs.
PAGE 52
AD9511 Reg. Addr.
PAGE 53
AD9511 Reg. Addr. (Hex) 58 Bit(s) Name <2> Soft SYNC 58 <3> 58 58 Dist Ref PowerDown <4> SYNC PowerDown <6:5> FUNCTION Pin Select 58 59 5A <7> <7:0> <0> Update Registers 5A END <7:1> Description Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit’s polarity is reversed. That is, a high level forces selected outputs into a known state, and a high > low transition triggers a sync (Default = 0b).
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AD9511 POWER SUPPLY The AD9511 requires a 3.3 V ± 5% power supply for VS. The tables in the Specifications section give the performance expected from the AD9511 with the power supply voltage within this range. The absolute maximum range of −0.3 V to +3.6 V, with respect to GND, must never be exceeded on the VS pin. Good engineering practice should be followed in the layout of power supply traces and ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 μF).
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AD9511 APPLICATIONS USING THE AD9511 OUTPUTS FOR ADC CLOCK APPLICATIONS level, termination) should be considered when selecting the best clocking/converter solution. Any high speed analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer; any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output.
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AD9511 Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9511 offers both LVPECL and LVDS outputs, which are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
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AD9511 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 12° MAX PIN 1 INDICATOR 48 1 EXPOSED PAD 6.75 BSC SQ 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 25 24 12 13 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 59.
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AD9511 NOTES Rev.
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AD9511 NOTES Rev.