Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9512BCPZ

1.2 GHz Clock Distribution IC, 1.6 GHz Inputs,

Dividers, Delay Adjust, Five Outputs

AD9512

Rev. A

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FEATURES

Two 1.6 GHz, differential clock inputs

5 programmable dividers, 1 to 32, all integers

Phase select for output-to-output coarse delay adjust

3 independent 1.2 GHz LVPECL outputs

Additive output jitter 225 fs rms

2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter 275 fs rms

Fine delay adjust on 1 LVDS/CMOS output

Serial control port

Space-saving 48-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

FUNCTIONAL BLOCK DIAGRAM

05287-001

SYNC

STATUS

SYNC

STATUS

SCLK

SDIO

SDO

CSB

SERIAL

CONTROL

PORT

FUNCTION

SYNCB,

RESETB

PDB

DSYNC

DSYNCB

DETECT

SYNC

VREF

RSET

AD9512

GNDVS

CLK1

CLK1B

CLK2

CLK2B

PROGRAMMABLE

DIVIDERS AND

PHASE ADJUST

OUT0

OUT0B

LVPECL

/1, /2, /3... /31, /32

OUT1

OUT1B

LVPECL

/1, /2, /3... /31, /32

OUT2

OUT2B

LVPECL

/1, /2, /3... /31, /32

OUT3

OUT3B

LVDS/CMOS

/1, /2, /3... /31, /32

OUT4

OUT4B

LVDS/CMOS

/1, /2, /3... /31, /32

DELAY

ADJUST

Figure 1.

GENERAL DESCRIPTION

The AD9512 provides a multi-output clock distribution in a

design that emphasizes low jitter and low phase noise to

maximize data converter performance. Other applications with

demanding phase noise and jitter requirements can also benefit

from this part.

There are five independent clock outputs. Three outputs are

LVPECL (1.2 GHz), and two are selectable as either LVDS

(800 MHz) or CMOS (250 MHz) levels.

Each output has a programmable divider that may be bypassed

or set to divide by any integer up to 32. The phase of one clock

output relative to another clock output may be varied by means

of a divider phase select function that serves as a coarse timing

adjustment.

One of the LVDS/CMOS outputs features a programmable

delay element with a range of up to 10 ns of delay. This fine

tuning delay block has 5-bit resolution, giving 32 possible delays

from which to choose.

The AD9512 is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9512 is available in a 48-lead LFCSP and can be

operated from a single 3.3 V supply. The temperature range is

−40°C to +85°C.

Summary of content (48 pages)

PAGE 1
.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs AD9512 FEATURES FUNCTIONAL BLOCK DIAGRAM VS FUNCTION DSYNC DSYNCB SYNCB, RESETB PDB DETECT SYNC GND RSET VREF AD9512 PROGRAMMABLE DIVIDERS AND PHASE ADJUST OUT0 OUT0B LVPECL OUT1 /1, /2, /3... /31, /32 OUT1B CLK1 LVPECL CLK1B OUT2 /1, /2, /3... /31, /32 OUT2B CLK2 LVDS/CMOS OUT3 /1, /2, /3...
PAGE 2
AD9512 TABLE OF CONTENTS Specifications..................................................................................... 4 Outputs ........................................................................................ 30 Clock Inputs .................................................................................. 4 Power-Down Modes .................................................................. 31 Clock Outputs ...............................................................................
PAGE 3
AD9512 LVPECL Clock Distribution......................................................45 LVDS Clock Distribution...........................................................45 Power and Grounding Considerations and Power Supply Rejection.......................................................................................45 Outline Dimensions........................................................................46 Ordering Guide ...........................................................................
PAGE 4
AD9512 SPECIFICATIONS Typical (Typ) is given for VS = 3.3 V ± 5%; TA = 25°C, RSET = 4.12 kΩ, unless otherwise noted. Minimum (Min) and Maximum (Max) values are given over full VS and TA (−40°C to +85°C) variation. CLOCK INPUTS Table 1. Parameter CLOCK INPUTS (CLK1, CLK2) 1 Input Frequency Input Sensitivity Min Typ 0 Unit 1.6 GHz mV p-p 150 2 Input Level Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Max 1.5 1.3 4.
PAGE 5
AD9512 TIMING CHARACTERISTICS Table 3.
PAGE 6
AD9512 Parameter DELAY ADJUST Shortest Delay Range 4 Zero Scale Full Scale Linearity, DNL Linearity, INL Longest Delay Range4 Zero Scale Full Scale Linearity, DNL Linearity, INL Delay Variation with Temperature Long Delay Range, 10 ns 5 Zero Scale Full Scale Short Delay Range, 1 ns5 Zero Scale Full Scale Min Typ Max Unit 0.05 0.72 0.36 1.12 0.5 0.8 0.68 1.51 ns ns LSB LSB 0.20 9.0 0.57 10.2 0.3 0.6 0.95 11.6 ns ns LSB LSB 0.35 −0.14 ps/°C ps/°C 0.51 0.
PAGE 7
AD9512 CLOCK OUTPUT PHASE NOISE Table 4. Parameter CLK1-TO-LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 38.
PAGE 8
AD9512 Parameter CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 491.52 MHz, OUT = 245.
PAGE 9
AD9512 Parameter CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1-TO-CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset > 10 MHz Offset CLK1 = 245.76 MHz, OUT = 61.
PAGE 10
AD9512 CLOCK OUTPUT ADDITIVE TIME JITTER Table 5. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 155.
PAGE 11
AD9512 Parameter CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 LVDS (OUT3) = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs Off) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs Off) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs On) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) =
PAGE 12
AD9512 Parameter DELAY BLOCK ADDITIVE TIME JITTER 1 100 MHz Output Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000 Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111 Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000 Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111 Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000 Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111 Delay FS = 4 ns (400 μA, 4C) Fine Adj. 00000 Delay FS = 4 ns (400 μA, 4C) Fine Adj. 11111 Delay FS = 5 ns (200 μA, 1C) Fine Adj. 00000 Delay FS = 5 ns (200 μA, 1C) Fine Adj.
PAGE 13
AD9512 FUNCTION PIN Table 7. Parameter INPUT CHARACTERISTICS Min Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low SYNC TIMING Pulse Width Low 2.0 Typ Max 0.8 110 1 2 Unit Test Conditions/Comments The FUNCTION pin has a 30 kΩ internal pull-down resistor. This pin should normally be held high. Do not leave NC. V V μA μA pF 50 ns 1.5 High speed clock cycles High speed clock is CLK1 or CLK2, whichever is being used for distribution.
PAGE 14
AD9512 POWER Table 9.
PAGE 15
AD9512 TIMING DIAGRAMS tCLK1 CLK1 DIFFERENTIAL tPECL 80% LVDS tLVDS tCMOS tRL tFL 05287-065 05287-002 20% Figure 4. LVDS Timing, Differential Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode SINGLE-ENDED DIFFERENTIAL 80% 80% CMOS 3pF LOAD LVPECL tFP 05287-064 tRP tRC tFC Figure 5. CMOS Timing, Single-Ended, 3 pF Load Figure 3. LVPECL Timing, Differential Rev.
PAGE 16
AD9512 ABSOLUTE MAXIMUM RATINGS Table 10. Parameter or Pin VS DSYNC/DSYNCB RSET CLK1, CLK1B, CLK2, CLK2B CLK1 CLK2 SCLK, SDIO, SDO, CSB OUT0, OUT1, OUT2, OUT3, OUT4 FUNCTION SYNC STATUS Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to GND GND GND GND CLK1B CLK2B GND GND Min −0.3 −0.3 −0.3 −0.3 −1.2 −1.2 −0.3 −0.3 Max +3.6 VS + 0.3 VS + 0.3 VS + 0.3 +1.2 +1.2 VS + 0.3 VS + 0.3 Unit V V V V V V V V GND GND −0.3 −0.3 VS + 0.3 VS + 0.
PAGE 17
AD9512 48 47 46 45 44 43 42 41 40 39 38 37 VS VS GND RSET VS GND OUT0 OUT0B VS VS GND GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9512 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 VS OUT3 OUT3B VS VS OUT4 OUT4B VS VS OUT1 OUT1B VS 05287-003 STATUS SCLK SDIO SDO CSB VS GND OUT2B OUT2 VS VS GND DNC = DO NO CONNECT PIN 1 INDICATOR 13 14 15 16 17 18 19 20 21 22 23 24 DSYNC 1 DSYNCB 2 VS 3 VS 4 DNC 5 VS 6 CLK2 7 CLK2B 8 VS 9 CLK1 10 CLK1B 11 FUNCTION 12 Figure 6.
PAGE 18
AD9512 Table 11. Pin Function Descriptions Pin No. 1 2 3, 4, 6, 9, 18, 22, 23, 25, 28, 29, 32, 33, 36, 39, 40, 44, 47, 48 5 7 8 10 11 12 13 14 15 16 17 19, 24, 37, 38, 43, 46 20 21 26 27 30 31 34 35 41 42 45 Mnemonic DSYNC DSYNCB VS Description Detect Sync. Used for multichip synchronization. Detect Sync Complement. Used for multichip synchronization. Power Supply (3.3 V). DNC CLK2 CLK2B CLK1 CLK1B FUNCTION STATUS SCLK SDIO SDO CSB GND Do Not Connect. Clock Input. Complementary Clock Input.
PAGE 19
AD9512 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 degrees to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.
PAGE 20
AD9512 TYPICAL PERFORMANCE CHARACTERISTICS 0.6 0.7 DEFAULT – 3 LVPECL + 2 LVDS (DIV ON) POWER (W) 0.6 POWER (W) 0.5 3 LVPECL + 2 LVDS (DIV BYPASSED) 0.4 3 LVPECL + 2 CMOS (DIV ON) 0.5 0.3 0 400 OUTPUT FREQUENCY (MHz) 800 05287-081 2 LVDS (DIV ON) 05287-080 3 LVPECL (DIV ON) 0.4 0 Figure 7. Power vs. Frequency—LVPECL, LVDS 40 60 80 OUTPUT FREQUENCY (MHz) 100 120 Figure 9. Power vs.
PAGE 21
AD9512 DIFFERENTIAL SWING (V p-p) 1.8 1.7 1.6 1.5 1.4 VERT 500mV/DIV 05287-056 05287-053 1.3 1.2 100 HORIZ 500ps/DIV 600 1100 1600 OUTPUT FREQUENCY (MHz) Figure 11. LVPECL Differential Output @ 800 MHz Figure 14. LVPECL Differential Output Swing vs. Frequency VERT 100mV/DIV 700 650 600 550 500 100 HORIZ 500ps/DIV 05287-050 05287-054 DIFFERENTIAL SWING (mV p-p) 750 300 500 700 900 OUTPUT FREQUENCY (MHz) Figure 12. LVDS Differential Output @ 800 MHz Figure 15.
PAGE 22
–110 –120 –120 –130 –130 –140 –140 –150 –150 –160 –160 –170 10 100 1k 10k 100k 1M 05287-052 L(f) (dBc/Hz) –110 05287-051 L(f) (dBc/Hz) AD9512 –170 10 10M 100 1k OFFSET (Hz) –80 –90 –90 –100 –100 –110 –110 –120 –130 –130 –140 –150 –150 –160 10k 100k 1M –160 –170 10 10M 100 1k OFFSET (Hz) –110 –120 –120 –130 –140 10M –130 –140 –150 –150 –160 –160 10k 1M 100k 1M 10M –170 10 OFFSET (Hz) 05287-046 L(f) (dBc/Hz) –110 05287-045 L(f) (dBc/Hz) –
PAGE 23
AD9512 VS FUNCTION DSYNC DSYNCB SYNCB, RESETB PDB DETECT SYNC GND RSET VREF AD9512 PROGRAMMABLE DIVIDERS AND PHASE ADJUST SYNC STATUS SYNC STATUS LVPECL OUT0 /1, /2, /3... /31, /32 OUT0B LVPECL OUT1 /1, /2, /3... /31, /32 OUT1B CLK1 LVPECL CLK1B OUT2 /1, /2, /3... /31, /32 OUT2B CLK2 LVDS/CMOS CLK2B OUT3 /1, /2, /3... /31, /32 OUT3B SCLK SDO SERIAL CONTROL PORT LVDS/CMOS /1, /2, /3... /31, /32 CSB ΔT DELAY ADJUST Figure 23.
PAGE 24
AD9512 FUNCTIONAL DESCRIPTION OVERALL SYNCB: 58h<6:5> = 01b Figure 23 shows a block diagram of the AD9512. The AD9512 accepts inputs on either of two clock inputs (CLK1 or CLK2). This clock can be divided by any integer value from 1 to 32. The duty cycle and relative phase of the outputs can be selected. There are three LVPECL outputs (OUT0, OUT1, OUT2) and two outputs that can be either LVDS or CMOS level outputs (OUT3, OUT4). OUT4 can also make use of a variable delay block.
PAGE 25
AD9512 DIVIDERS Example 2: Each of the five clock outputs of the AD9512 has its own divider. The divider can be bypassed to get an output at the same frequency as the input (1×). When a divider is bypassed, it is powered down to save power. All integer divide ratios from 1 to 32 may be selected. A divide ratio of 1 is selected by bypassing the divider. Each divider can be configured for divide ratio, phase, and duty cycle.
PAGE 26
AD9512 4Ah to 52h Divide Ratio 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 Duty Cycle (%) 67 33 78 22 89 11 50 60 40 70 30 80 20 90 10 55 45 64 36 73 27 82 18 91 9 50 58 42 67 33 75 25 83 17 92 8 54 46 62 38 69 31 77 23 85 15 92 8 50 57 43 LO<7:4> 2 5 1 6 0 7 4 3 5 2 6 1 7 0 8 4 5 3 6 2 7 1 8 0 9 5 4 6 3 7 2 8 1 9 0 A 5 6 4 7 3 8 2 9 1 A 0 B 6 5 7 4Ah to 52h HI<3:0> 5 2 6 1 7 0 4 5 3 6 2 7 1 8 0 5 4 6
PAGE 27
AD9512 4Ah to 52h Divide Ratio 17 17 17 17 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 19 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 21 21 21 21 21 Duty Cycle (%) 88 12 94 6 50 56 44 61 39 67 33 72 28 78 22 83 17 89 11 53 47 58 42 63 37 68 32 74 26 79 21 84 16 50 55 45 60 40 65 35 70 30 75 25 80 20 52 48 57 43 62 LO<7:4> 1 E 0 F 8 7 9 6 A 5 B 4 C 3 D 2 E 1 F 8 9 7 A 6 B 5 C 4 D 3 E 2 F 9 8 A 7 B 6 C 5 D 4 E 3 F 9 A 8 B 7 4Ah to 52h HI<3:0> E 1 F 0 8 9 7 A 6 B 5 C 4 D
PAGE 28
AD9512 4Ah to 52h Divide Ratio 26 27 27 27 27 27 27 28 28 28 28 28 Duty Cycle (%) 38 52 48 56 44 59 41 50 54 46 57 43 LO<7:4> F C D B E A F D C E B F 4Ah to 52h HI<3:0> 9 D C E B F A D E C F B Divide Ratio 29 29 29 29 30 30 30 31 31 32 Rev.
PAGE 29
AD9512 Divider Phase Offset The phase of each output may be selected, depending on the divide ratio chosen. This is selected by writing the appropriate values to the registers, which set the phase and start high/low bit for each output. These are the odd numbered registers from 4Bh to 53h. Each divider has a 4-bit phase offset <3:0> and a start high or low bit <4>.
PAGE 30
AD9512 DIV = 18 Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 Phase offsets may be related to degrees by calculating the phase step for a particular divide ratio: Phase Step = 360°/(Divide Ratio) = 360°/DIV This path adds some jitter greater than that specified for the nondelay outputs. This means that the delay function should be used primarily for clocking digital chips, such as FPGA, ASIC, DUC, and DDC, rather than for data converters.
PAGE 31
AD9512 the LVPECL power-down mode is set to <11b>, the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions. 3.5mA Individual Clock Output Power-Down OUTB Any of the five clock distribution outputs may be powered down individually by writing to the appropriate registers via the SCP. The register map details the individual power-down settings for each output. The LVDS/CMOS outputs may be powered down, regardless of their output load configuration.
PAGE 32
AD9512 slave must provide this same frequency back to the DSYNCB input of the slave. SINGLE-CHIP SYNCHRONIZATION SYNCB—Hardware SYNC The AD9512 clocks can be synchronized to each other at any time. The outputs of the clocks are forced into a known state with respect to each other and then allowed to continue clocking from that state in synchronicity. Before a synchronization is done, the FUNCTION Pin must be set as the input (58h<6:5> = 01b).
PAGE 33
AD9512 SERIAL CONTROL PORT The AD9512 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9512 serial control port is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The serial control port allows read/write access to all registers that configure the AD9512.
PAGE 34
AD9512 writing to Register 5Ah<0> = 1b. This update bit is self-clearing (it is not required to write 0 to it to clear it). Since any number of bytes of data can be changed before issuing an update command, the update simultaneously enables all register changes since any previous update. Phase offsets or divider synchronization will not become effective until a SYNC is issued (see the Single-Chip Synchronization section).
PAGE 35
AD9512 Table 15. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 = 0 A8 = 0 A7 = 0 A6 A5 A4 A3 A2 A1 A0 CSB SCLK DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16-BIT INSTRUCTION HEADER D7 D6 D5 D4 D3 D2 D1 D0 D7 REGISTER (N) DATA D6 D5 D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 05287-019 SDIO DON'T CARE DON'T CARE Figure 32.
PAGE 36
AD9512 tS tH CSB tCLK tHI tLO tDS SCLK SDIO BI N 05287-040 tDH BI N + 1 Figure 37. Serial Control Port Timing—Write Table 16.
PAGE 37
AD9512 REGISTER MAP AND DESCRIPTION SUMMARY TABLE Table 17. AD9512 Register Map Addr (Hex) 00 Parameter Serial Control Port Configuration Bit 7 (MSB) SDO Inactive (Bidirectional Mode) Bit 6 LSB First Bit 5 Soft Reset Bit 4 Long Instruction Bit 3 Bit 2 Bit 1 Not Used Bit 0 (LSB) Def.
PAGE 38
AD9512 Addr (Hex) 4F Parameter Divider 2 50 51 Divider 3 Divider 3 Bypass 52 53 Divider 4 Divider 4 Bypass Bit 7 (MSB) Bypass Bit 6 Bit 5 Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync 59 5A Bit 3 Bit 2 Bit 1 Phase Offset <3:0> Def.
PAGE 39
AD9512 REGISTER MAP DESCRIPTION Table 18 lists the AD9512 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 18 describes the functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 17. Table 18. AD9512 Register Descriptions Reg. Addr.
PAGE 40
AD9512 Reg. Addr. (Hex) 36 Bit(s) <5:1> Name Delay Fine Adjust OUT4 36 <7:6> 37 (38) <7:0> (39) (3A) (3B) (3C) 3D (3E) (3F) 3D (3E) (3F) <1:0> <3:2> Not Used. Not Used. OUTPUTS Power-Down LVPECL OUT0 (OUT1) (OUT2) Output Level LVPECL OUT0 (OUT1) (OUT2) <7:4> 3D (3E) (3F) 40 (41) <0> 40 (41) <2:1> 40 (41) <3> 40 (41) <4> 40 (41) <7:5> Description Sets Delay Within Full Scale of the Ramp; There Are 32 Steps. 00000b => Zero Delay (Default). 11111b => Maximum Delay.
PAGE 41
AD9512 Reg. Addr. (Hex) Bit(s) Name CLK1 AND CLK2 Description 45 <0> Clock Select 45 45 45 <1> <2> <4:3> CLK1 Power-Down CLK2 Power-Down 0: CLK2 Drives Distribution Section. 1: CLK1 Drives Distribution Section (Default). 1 = CLK1 Input Is Powered Down (Default = 0b). 1 = CLK2 Input Is Powered Down (Default = 0b). Not Used. 45 <5> All Clock Inputs Power- 1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree; Down (Default = 0b). Not Used. Not Used.
PAGE 42
AD9512 Reg. Addr. (Hex) Bit(s) <7> 4B (4D) (4F) (51) (53) 54 (55) <7:0> (56) (57) Name Bypass Divider OUT0 (OUT1) (OUT2) (OUT3) (OUT4) Description Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b). Not Used. FUNCTION 58 <0> SYNC Detect Enable 1 = Enable SYNC Detect (Default = 0b). 58 <1> SYNC Select 58 <2> Soft SYNC 58 <3> Dist Ref Power-Down 1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles.
PAGE 43
AD9512 POWER SUPPLY The AD9512 requires a 3.3 V ± 5% power supply for VS. The tables in the Specifications section give the performance expected from the AD9512 with the power supply voltage within this range. The absolute maximum range of −0.3 V to +3.6 V, with respect to GND, must never be exceeded on the VS pin. Good engineering practice should be followed in the layout of power supply traces and ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 μF).
PAGE 44
AD9512 APPLICATIONS USING THE AD9512 OUTPUTS FOR ADC CLOCK APPLICATIONS level, termination) should be considered when selecting the best clocking/converter solution. Any high speed analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer; any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output.
PAGE 45
AD9512 Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9512 offers both LVPECL and LVDS outputs, which are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
PAGE 46
AD9512 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 12° MAX PIN 1 INDICATOR 48 1 EXPOSED PAD 6.75 BSC SQ 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 25 24 12 13 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 45.
PAGE 47
AD9512 NOTES Rev.