Datasheet

AD9512
Rev. A | Page 12 of 48
Parameter Min Typ Max Unit Test Conditions/Comments
DELAY BLOCK ADDITIVE TIME JITTER
1
Incremental additive jitter
1
100 MHz Output
Delay FS = 1 ns (1600 A, 1C) Fine Adj. 00000 0.61 ps
Delay FS = 1 ns (1600 A, 1C) Fine Adj. 11111 0.73 ps
Delay FS = 2 ns (800 A, 1C) Fine Adj. 00000 0.71 ps
Delay FS = 2 ns (800 A, 1C) Fine Adj. 11111 1.2 ps
Delay FS = 3 ns (800 A, 4C) Fine Adj. 00000 0.86 ps
Delay FS = 3 ns (800 A, 4C) Fine Adj. 11111 1.8 ps
Delay FS = 4 ns (400 A, 4C) Fine Adj. 00000 1.2 ps
Delay FS = 4 ns (400 A, 4C) Fine Adj. 11111 2.1 ps
Delay FS = 5 ns (200 A, 1C) Fine Adj. 00000 1.3 ps
Delay FS = 5 ns (200 A, 1C) Fine Adj. 11111 2.7 ps
Delay FS = 11 ns (200 A, 4C) Fine Adj. 00000 2.0 ps
Delay FS = 11 ns (200 A, 4C) Fine Adj. 00100 2.8 ps
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SERIAL CONTROL PORT
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
CSB, SCLK (INPUTS)
CSB and SCLK have 30 kΩ
internal pull-down resistors
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 110 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
SDIO (WHEN INPUT)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 10 nA
Input Logic 0 Current 10 nA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/t
SCLK
) 25 MHz
Pulse Width High, t
PWH
16 ns
Pulse Width Low, t
PWL
16 ns
SDIO to SCLK Setup, t
DS
2 ns
SCLK to SDIO Hold, t
DH
1 ns
SCLK to Valid SDIO and SDO, t
DV
6 ns
CSB to SCLK Setup and Hold, t
S
, t
H
2 ns
CSB Minimum Pulse Width High, t
PWH
3 ns