Datasheet

AD9512
Rev. A | Page 15 of 48
TIMING DIAGRAMS
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C
LK1
t
CMOS
t
CLK1
t
LVDS
t
PECL
Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode
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DIFFERENTIAL
LVPECL
80%
20%
t
RP
t
FP
Figure 3. LVPECL Timing, Differential
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DIFFERENTIAL
LVDS
80%
20%
t
RL
t
FL
Figure 4. LVDS Timing, Differential
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SINGLE-ENDED
CMOS
3pF LOAD
80%
20%
t
RC
t
FC
Figure 5. CMOS Timing, Single-Ended, 3 pF Load