Datasheet

AD9512
Rev. A | Page 37 of 48
REGISTER MAP AND DESCRIPTION
SUMMARY TABLE
Table 17. AD9512 Register Map
Addr
(Hex)
Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Def.
Value
(Hex)
Notes
00
Serial
Control Port
Configuration
SDO Inactive
(Bidirectional
Mode)
LSB
First
Soft
Reset
Long
Instruction
Not Used 10
01 to
33
Not Used
FINE DELAY
ADJUST
Fine
Delays
Bypassed
34 Delay Bypass 4 Not Used Bypass 01
Bypass
Delay
35
Delay
Full-Scale 4
Not Used Ramp Capacitor <5:3> Ramp Current <2:0> 00
Max. Delay
Full-Scale
36
Delay Fine
Adjust 4
Not Used 5-Bit Fine Delay <5:1> Not Used 00
Min. Delay
Value
37, 38,
39, 3A,
3B, 3C
Not Used
OUTPUTS
3D LVPECL OUT0 Not Used
Output Level
<3:2>
Power-Down
<1:0>
08 ON
3E LVPECL OUT1 Not Used
Output Level
<3:2>
Power-Down
<1:0>
08 ON
3F LVPECL OUT2 Not Used
Output Level
<3:2>
Power-Down
<1:0>
08 ON
40
LVDS_CMOS
OUT 3
Not Used
CMOS
Inverted
Driver On
Logic
Select
Output Level
<2:1>
Output
Power
02 LVDS, ON
41
LVDS_CMOS
OUT 4
Not Used
CMOS
Inverted
Driver On
Logic
Select
Output Level
<2:1>
Output
Power
02 LVDS, ON
42, 43,
44
Not Used
CLK1 AND
CLK2
Input
Receivers
45
Clocks Select,
Power-Down
(PD) Options
Not Used
CLKs
in
PD
Not Used
Not
Used
CLK2
PD
CLK1
PD
Select
CLK IN
01
All Clocks
ON, Select
CLK1
46, 47,
48, 49
Not Used
DIVIDERS
4A Divider 0 Low Cycles <7:4> High Cycles <3:0> 00 Divide by 2
4B Divider 0 Bypass
No
Sync
Force Start H/L Phase Offset <3:0> 00 Phase = 0
4C Divider 1 Low Cycles <7:4> High Cycles <3:0> 11 Divide by 4
4D Divider 1 Bypass
No
Sync
Force Start H/L Phase Offset <3:0> 00 Phase = 0
4E Divider 2 Low Cycles <7:4> High Cycles <3:0> 33 Divide by 8