Datasheet

AD9512
Rev. A | Page 40 of 48
Reg.
Addr.
(Hex)
Bit(s) Name Description
36 <5:1>
Delay Fine Adjust
OUT4
Sets Delay Within Full Scale of the Ramp; There Are 32 Steps.
00000b => Zero Delay (Default).
11111b => Maximum Delay.
36 <7:6> Not Used.
37 (38)
(39)
(3A) (3B)
(3C)
<7:0> Not Used.
OUTPUTS
3D (3E)
(3F)
<1:0>
Power-Down LVPECL
OUT0
(OUT1)
(OUT2)
Mode <1> <0> Description Output
ON 0 0 Normal Operation. ON
PD1 0 1 Test Only—Do Not Use. OFF
PD2 1 0
Safe Power-Down.
Partial Power-Down; Use If Output Has
Load Resistors.
OFF
PD3 1 1
Total Power-Down.
Use Only If Output Has No Load Resistors.
OFF
Output Single-Ended Voltage Levels for LVPECL Outputs.
3D (3E)
(3F)
<3:2>
Output Level LVPECL
OUT0
(OUT1)
(OUT2)
<3> <2> Output Voltage (mV)
0 0 490
0 1 330
1 0 805 (Default)
1 1 650
3D (3E)
(3F)
<7:4> Not Used.
40 (41) <0>
Power-Down
LVDS/CMOS
OUT3
(OUT4)
Power-Down Bit for Both Output and LVDS Driver.
0 = LVDS/CMOS on (Default).
1 = LVDS/CMOS Power-Down.
40 (41) <2:1>
Output Current Level
LVDS
OUT3
(OUT4)
<2> <1> Current (mA) Termination (Ω)
0 0 1.75 100
0 1 3.5 (Default) 100
1 0 5.25 50
1 1 7 50
40 (41) <3>
LVDS/CMOS Select
OUT3
(OUT4)
0 = LVDS (Default).
1 = CMOS.
40 (41) <4>
Inverted CMOS Driver
OUT3
(OUT4)
Affects Output Only when in CMOS Mode.
0 = Disable Inverted CMOS Driver (Default).
1 = Enable Inverted CMOS Driver.
40 (41) <7:5> Not Used.