Datasheet

AD9512
Rev. A | Page 41 of 48
Reg.
Addr.
(Hex)
Bit(s) Name Description
CLK1 AND CLK2
45 <0> Clock Select
0: CLK2 Drives Distribution Section.
1: CLK1 Drives Distribution Section (Default).
45 <1> CLK1 Power-Down 1 = CLK1 Input Is Powered Down (Default = 0b).
45 <2> CLK2 Power-Down 1 = CLK2 Input Is Powered Down (Default = 0b).
45 <4:3> Not Used.
45 <5>
All Clock Inputs Power-
Down
1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree;
(Default = 0b).
45 <7:6> Not Used.
46 (47)
(48) (49)
<7:0> Not Used.
DIVIDERS
<3:0> Divider High Number of Clock Cycles Divider Output Stays High.
4A OUT0
(4C) (OUT1)
(4E) (OUT2)
(50) (OUT3)
(52) (OUT4)
<7:4> Divider Low Number of Clock Cycles Divider Output Stays Low.
4A OUT0
(4C) (OUT1)
(4E) (OUT2)
(50) (OUT3)
(52) (OUT4)
<3:0> Phase Offset Phase Offset (Default = 0000b).
4B OUT0
(4D) (OUT1)
(4F) (OUT2)
(51) (OUT3)
(53) (OUT4)
<4> Start Selects Start High or Start Low.
4B OUT0 (Default = 0b).
(4D) (OUT1)
(4F) (OUT2)
(51) (OUT3)
(53) (OUT4)
<5> Force
Forces Individual Outputs to the State Specified in Start (Above).
This Function Requires That Nosync (Below) Also Be Set (Default = 0b).
4B OUT0
(4D) (OUT1)
(4F) (OUT2)
(51) (OUT3)
(53) (OUT4)
<6> Nosync Ignore Chip-Level Sync Signal (Default = 0b).
4B OUT0
(4D) (OUT1)
(4F) (OUT2)
(51) (OUT3)
(53) (OUT4)