Datasheet

AD9512
Rev. A | Page 42 of 48
Reg.
Addr.
(Hex)
Bit(s) Name Description
<7> Bypass Divider Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b).
4B OUT0
(4D) (OUT1)
(4F) (OUT2)
(51) (OUT3)
(53) (OUT4)
54 (55)
(56) (57)
<7:0> Not Used.
FUNCTION
58 <0> SYNC Detect Enable 1 = Enable SYNC Detect (Default = 0b).
58 <1> SYNC Select
1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles.
0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles.
58 <2> Soft SYNC
Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit’s
polarity is reversed. That is, a high level forces selected outputs into a known state, and a high >
low transition triggers a sync (Default = 0b).
58 <3> Dist Ref Power-Down 1 = Power-Down the References for the Distribution Section (Default = 0b).
58 <4> SYNC Power-Down 1 = Power-Down the SYNC (Default = 0b).
<6> <5> Function
0 0 RESETB (Default)
0 1 SYNCB
1 0 Test Only; Do Not Use
58 <6:5> FUNCTION Pin Select
1 1 PDB
58 <7> Not Used.
59 <7:0> Not Used.
5A <0> Update Registers
1 written to this bit updates all registers and transfers all serial control port register buffer
contents to the control registers on the next rising SCLK edge. This is a self-clearing bit. 0 does
not have to be written to clear it.
5A <7:1> Not Used.
END