Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9513BCPZ-REEL7

800 MHz Clock Distribution IC, Dividers,

Delay Adjust, Three Outputs

AD9513

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

1.6 GHz differential clock input

3 programmable dividers

Divide-by in range from1 to 32

Phase select for coarse delay adjust

Three 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter 300 fs rms

Time delays up to 11.6 ns

Device configured with 4-level logic pins

Space-saving, 32-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

ATE

FUNCTIONAL BLOCK DIAGRAM

05595-001

CLK

CLKB

SYNCB

RSET

SGND

AD9513

VREF S10S9S8S7S6S5S4S3S2S1S0

SETUP LOGIC

OUT0

/1. . . /32

LVDS/CMOS

OUT1

/1. . . /32

LVDS/CMOS

OUT2

/1. . . /32

LVDS/CMOS

∆

Figure 1.

GENERAL DESCRIPTION

The AD9513 features a three-output clock distribution IC in a

design that emphasizes low jitter and phase noise to maximize

data converter performance. Other applications with

demanding phase noise and jitter requirements also benefit

from this part.

There are three independent clock outputs that can be set to

either LVDS or CMOS levels. These outputs operate to

800 MHz in LVDS mode and to 250 MHz in CMOS mode.

Each output has a programmable divider that can be set to

divide by a selected set of integers ranging from 1 to 32. The

phase of one clock output relative to the other clock output can

be set by means of a divider phase select function that serves as

a coarse timing adjustment.

One of the outputs features a delay element with three selectable

full-scale delay values (1.8 ns, 6.0 ns, and 11.6 ns), each with

16 steps of fine adjustment.

The AD9513 does not require an external controller for

operation or setup. The device is programmed by means of

11 pins (S0 to S10) using 4-level logic. The programming pins

are internally biased to ⅓ V

. The VREF pin provides a level of

⅔ V

. V

(3.3 V) and GND (0 V) provide the other two logic levels.

The AD9513 is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9513 is available in a 32-lead LFCSP and operates from

a single 3.3 V supply. The temperature range is −40°C to +85°C.

Summary of content (28 pages)

PAGE 1
800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs AD9513 FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust Three 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 300 fs rms Time delays up to 11.6 ns Device configured with 4-level logic pins Space-saving, 32-lead LFCSP FUNCTIONAL BLOCK DIAGRAM RSET VS GND AD9513 LVDS/CMOS OUT0 /1. . . /32 OUT0B LVDS/CMOS CLK OUT1 /1. . .
PAGE 2
AD9513 TABLE OF CONTENTS Features .............................................................................................. 1 Power-On SYNC .................................................................... 17 Applications....................................................................................... 1 SYNCB..................................................................................... 17 Functional Block Diagram ..............................................................
PAGE 3
AD9513 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; TA = 25°C, RSET = 4.12 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. CLOCK INPUT Table 1. Parameter CLOCK INPUT (CLK) Input Frequency Input Sensitivity 1 Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Min Typ 0 1.5 1.3 4.0 150 1.6 150 4.8 2 Max Unit 1.
PAGE 4
AD9513 TIMING CHARACTERISTICS CLK input slew rate = 1 V/ns or greater. Table 3.
PAGE 5
AD9513 Parameter S0 = 1 Zero-Scale Delay Time3 Zero-Scale Variation with Temperature Full-Scale Time Delay3 Full-Scale Variation with Temperature Linearity, DNL Linearity, INL 1 2 3 Min Typ Max 0.59 0.47 11.6 −5 0.2 0.2 Unit Test Conditions/Comments ns ps/°C ns ps/°C LSB LSB This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.
PAGE 6
AD9513 CLOCK OUTPUT PHASE NOISE Table 4. Parameter CLK-TO-LVDS ADDITIVE PHASE NOISE CLK = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 491.52 MHz, OUT = 245.
PAGE 7
AD9513 Parameter CLK = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK-TO-CMOS ADDITIVE PHASE NOISE CLK = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 245.76 MHz, OUT = 61.
PAGE 8
AD9513 CLOCK OUTPUT ADDITIVE TIME JITTER Table 5.
PAGE 9
AD9513 Parameter DELAY BLOCK ADDITIVE TIME JITTER 1 Delay FS = 1.8 ns Fine Adj. 00000 Delay FS = 1.8 ns Fine Adj. 11111 Delay FS = 6.0 ns Fine Adj. 00000 Delay FS = 6.0 ns Fine Adj. 11111 Delay FS = 11.6 ns Fine Adj. 00000 Delay FS = 11.6 ns Fine Adj. 11111 1 Min Typ Max Unit 0.71 1.2 1.3 2.7 2.0 2.8 Test Conditions/Comments 100 MHz output; incremental additive jitter1 ps rms ps rms ps rms ps rms ps rms ps rms This value is incremental.
PAGE 10
AD9513 TIMING DIAGRAMS tCLK CLK SINGLE-ENDED 80% CMOS 3pF LOAD tLVDS tCMOS Figure 2. CLK/CLKB to Clock Output Timing, DIV = 1 Mode 80% LVDS 05595-065 20% tFL tFC Figure 4. CMOS Timing, Single-Ended, 3 pF Load DIFFERENTIAL tRL tRC Figure 3. LVDS Timing, Differential Rev.
PAGE 11
AD9513 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter or Pin VS RSET CLK CLK OUT0, OUT1, OUT2 FUNCTION STATUS Junction Temperature 1 Storage Temperature Lead Temperature (10 sec) With Respect to GND GND GND CLKB GND GND GND Min −0.3 −0.3 −0.3 −1.2 −0.3 −0.3 −0.3 −65 Max +3.6 VS + 0.3 VS + 0.3 +1.2 VS + 0.3 VS + 0.3 VS + 0.3 150 +150 300 Unit V V V V V V V °C °C °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 12
AD9513 25 S0 27 OUT0B 26 VS 29 VS 28 OUT0 30 VS 32 RSET 31 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VS 1 THE EXPOSED PADDLE IS AN ELECTRICAL AND THERMAL CONNECTION 24 VS CLK 2 23 OUT1 CLKB 3 VS 4 1 21 VS TOP VIEW (Not to Scale) SYNCB 5 32 25 24 22 OUT1B AD9513 20 VS VREF 6 EXPOSED PAD (BOTTOM VIEW) GND 19 OUT2 S10 7 18 OUT2B S9 8 9 8 05595-006 17 16 05595-005 S1 16 S3 14 S2 15 S5 12 S4 13 S6 11 S8 9 S7 10 17 VS Figure 6. Exposed Paddle Figure 5.
PAGE 13
AD9513 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter.
PAGE 14
AD9513 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 0.7 3 LVDS (DIV ON) 0.6 3 CMOS (DIV ON) 0.5 POWER (W) POWER (W) 0.3 3 LVDS (DIV = 1) 0.4 3 CMOS (DIV OFF) 0.3 0.2 200 400 600 800 STOP 5GHz 05595-051 0 20 40 60 80 Figure 9. Power vs. Frequency—CMOS Figure 7. Power vs. Frequency—LVDS START 300kHz 0.1 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) 05595-097 0.1 05595-050 0.2 Figure 8. CLK Smith Chart (Evaluation Board) Rev.
PAGE 15
AD9513 HORIZ 500ps/DIV 700 650 600 550 500 100 300 500 700 05595-013 VERT 100mV/DIV 05595-010 DIFFERENTIAL SWING (mV p-p) 750 900 OUTPUT FREQUENCY (MHz) Figure 10. LVDS Differential Output @ 800 MHz Figure 12. LVDS Differential Output Swing vs. Frequency 3.5 2pF 3.0 OUTPUT (VPK) 2.5 10pF 2.0 1.5 1.0 HORIZ 1ns/DIV Figure 11. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 05595-011 VERT 500mV/DIV 0 0 100 200 300 400 500 600 OUTPUT FREQUENCY (MHz) Figure 13.
PAGE 16
–80 –90 –90 –100 –100 –110 –110 –120 –130 –120 –130 –140 –140 –150 –150 –160 –160 –170 10 100 1k 10k 100k 1M –170 10 10M 05595-049 L(f) (dBc/Hz) –80 05595-048 L(f) (dBc/Hz) AD9513 100 1k OFFSET (Hz) –100 –110 –110 –120 –120 –130 –140 –140 –150 –160 –160 10k 10M –130 –150 1k 1M 100k 1M 10M –170 10 OFFSET (Hz) 05595-046 L(f) (dBc/Hz) –100 100 100k Figure 16. Additive Phase Noise—LVDS DIV2, 122.88 MHz 05595-045 L(f) (dBc/Hz) Figure 14.
PAGE 17
AD9513 3.3V FUNCTIONAL DESCRIPTION 3.1V 2.2V OVERALL 35ms MAX VS 0V CLK CLOCK FREQUENCY IS EXAMPLE ONLY OUT DIVIDE = 2 PHASE = 0 OUT2 includes an analog delay block that can be set to add an additional delay of 1.8 ns, 6.0 ns, or 11.6 ns full scale, each with 16 levels of fine adjustment. < 65ms 05595-094 The AD9513 provides for the distribution of its input clock on up to three outputs. Each output can be set to either LVDS or CMOS logic levels.
PAGE 18
AD9513 Synchronization is initiated by pulling the SYNCB pin low for a minimum of 5 ns. The input clock does not have to be present at the time the command is issued. The synchronization occurs after four input clock cycles. The synchronization applies to clock outputs • that are not turned OFF • where the divider is not divide = 1 (divider bypassed) The AD9513 operation is determined by the combination of logic levels present at the setup pins.
PAGE 19
AD9513 Table 11. Output Delay Full Scale S0 0 1/3 2/3 1 Table 14. OUT2 Divide or OUT1 Phase Delay Bypass 1.8 ns 6.0 ns 11.6 ns Table 12.
PAGE 20
AD9513 Table 16.
PAGE 21
AD9513 DELAY BLOCK OUTPUTS OUT2 includes an analog delay element that gives variable time delays (ΔT) in the clock signal passing through that output. Each of the three AD9513 outputs can be selected either as LVDS differential outputs or as pairs of CMOS single-ended outputs. If selected as CMOS, the OUT is a noninverted, singleended output, and OUTB is an inverted, single-ended output. CLOCK INPUT OUT1 ONLY 3.
PAGE 22
AD9513 POWER MANAGEMENT POWER SUPPLY The AD9513 requires a 3.3 V ± 5% power supply for VS. The tables in the Specifications section give the performance expected from the AD9513 with the power supply voltage within this range. In no case should the absolute maximum range of −0.3 V to +3.6 V, with respect to GND, be exceeded on Pin VS. Good engineering practice should be followed in the layout of power supply traces and the ground plane of the PCB.
PAGE 23
AD9513 APPLICATIONS USING THE AD9513 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed, analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer; any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output.
PAGE 24
AD9513 Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9513 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 32. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.
PAGE 25
AD9513 PHASE NOISE AND JITTER MEASUREMENT SETUPS WENZEL OSCILLATOR EVALUATION BOARD ZFL1000VH2 SPLITTER ZESC-2-11 OUT1 TERM AMP OUT1B TERM +28dB CLK ATTENUATOR –12dB SIG IN ATTENUATOR –7dB REF IN 0° EVALUATION BOARD ZFL1000VH2 OUT1 TERM AMP OUT1B TERM +28dB CLK VARIABLE DELAY COLBY PDL30A 0.01ns STEP TO 10ns 05595-041 BALUN AD9513 Figure 33.
PAGE 26
AD9513 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX 25 24 PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 32 1 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 17 16 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 35.
PAGE 27
AD9513 NOTES Rev.