Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 23 of 80
–120
–130
–125
–135
–140
–145
–150
–155
–160
10 100M10M
1M100k
10k
1k100
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06420-026
Figure 31. Phase Noise (Additive) LVPECL at 245.76 MHz, Divide-by-1
–110
–120
–130
–140
–150
–160
10 100M10M
1M100k10k1k
100
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06420-027
Figure 32. Phase Noise (Additive) LVPECL at 200 MHz, Divide-by-5
–100
–110
–120
–130
–140
–150
10 100M10M1M
100k10k1k100
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06420-128
Figure 33. Phase Noise (Additive) LVPECL at 1600 MHz, Divide-by-1
–110
–160
–150
–140
–130
–120
10 100M
1k 10k
100k 1M
10M
100
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06420-142
Figure 34. Phase Noise (Additive) LVDS at 200 MHz, Divide-by-1
–100
–110
–120
–130
–140
–150
10
100M10M1M100k10k
1k100
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06420-130
Figure 35. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2
–120
–130
–140
–150
–160
–170
10 100M
10M1M100k10k1k
100
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06420-131
Figure 36. Phase Noise (Additive) CMOS at 50 MHz, Divide-by-20