Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
AD9516-1 Data Sheet
Rev. C | Page 56 of 80
Reg.
Addr.
(Hex)
Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
Fine Delay Adjust—OUT6 to OUT9
0x0A0
OUT6 delay
bypass
Blank
OUT6 delay
bypass
0x01
0x0A1
OUT6 delay
full-scale
Blank OUT6 ramp capacitors OUT6 ramp current 0x00
0x0A2
OUT6 delay
fraction
Blank
OUT6 delay fraction
0x00
0x0A3
OUT7 delay
bypass
Blank
OUT7 delay
bypass
0x01
0x0A4
OUT7 delay
full-scale
Blank OUT7 ramp capacitors OUT7 ramp current 0x00
0x0A5
OUT7 delay
fraction
Blank OUT7 delay fraction 0x00
0x0A6
OUT8 delay
bypass
Blank
OUT8 delay
bypass
0x01
0x0A7
OUT8 delay
full-scale
Blank OUT8 ramp capacitors OUT8 ramp current 0x00
0x0A8
OUT8 delay
fraction
Blank OUT8 delay fraction 0x00
0x0A9
OUT9 delay
bypass
Blank
OUT9 delay
bypass
0x01
0x0AA
OUT9 delay
full-scale
Blank OUT9 ramp capacitors OUT9 ramp current 0x00
0x0AB
OUT9 delay
fraction
Blank OUT9 delay fraction 0x00
0x0AC
to
0x0EF
Blank
LVPECL Outputs
0x0F0 OUT0 Blank
OUT0
invert
OUT0 LVPECL
differential voltage
OUT0 power-down 0x08
0x0F1 OUT1 Blank
OUT1
invert
OUT1 LVPECL
differential voltage
OUT1 power-down 0x0A
0x0F2 OUT2 Blank
OUT2
invert
OUT2 LVPECL
differential voltage
OUT2 power-down 0x08
0x0F3 OUT3 Blank
OUT3
invert
OUT3 LVPECL
differential voltage
OUT3 power-down 0x0A
0x0F4 OUT4 Blank
OUT4
invert
OUT4 LVPECL
differential voltage
OUT4 power-down 0x08
0x0F5 OUT5 Blank
OUT5
invert
OUT5 LVPECL
differential voltage
OUT5 power-down 0x0A
0x0F6
to
0x13F
Blank
LVDS/CMOS Outputs
0x140 OUT6
OUT6 CMOS
output polarity
OUT6 LVDS/
CMOS
output
polarity
OUT6
CMOS B
OUT6 select
LVDS/CMOS
OUT6 LVDS
output current
OUT6
power-down
0x42
0x141 OUT7
OUT7 CMOS
output polarity
OUT7 LVDS/
CMOS
output
polarity
OUT7
CMOS B
OUT7 select
LVDS/CMOS
OUT7 LVDS
output current
OUT7
power-down
0x43
0x142 OUT8
OUT8 CMOS
output polarity
OUT8 LVDS/
CMOS
output
polarity
OUT8
CMOS B
OUT8 select
LVDS/CMOS
OUT8 LVDS
output current
OUT8
power-down
0x42
0x143 OUT9
OUT9 CMOS
output polarity
OUT9 LVDS/
CMOS
output
polarity
OUT9
CMOS B
OUT9 select
LVDS/CMOS
OUT9 LVDS
output current
OUT9
power-down
0x43