Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9516-3BCPZ

14-Output Clock Generator with

Integrated 2.0 GHz VCO

Data Sheet

AD9516-3

Rev. C Document Feedback

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FEATURES

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 1.75 GHz to 2.25 GHz

External VCO/VCXO to 2.4 GHz optional

1 differential or 2 single-ended reference inputs

Reference monitoring capability

Automatic revertive and manual reference

switchover/holdover modes

Accepts LVPECL, LVDS, or CMOS references to 250 MHz

Programmable delays in path to PFD

Digital or analog lock detect, selectable

6 pairs of 1.6 GHz LVPECL outputs

Each output pair shares a 1-to-32 divider with coarse

phase delay

Additive output jitter: 225 fs rms

Channel-to-channel skew paired outputs of <10 ps

4 pairs of 800 MHz LVDS clock outputs

Each output pair shares two cascaded 1-to-32 dividers

with coarse phase delay

Additive output jitter: 275 fs rms

Fine delay adjust (Δt) on each LVDS output

Each LVDS output can be reconfigured as two 250 MHz

CMOS outputs

Automatic synchronization of all outputs on power-up

Manual output synchronization available

64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

10/40/100 Gb/sec networking line cards, including SONET,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

ATE and high performance instrumentation

GENERAL DESCRIPTION

The AD9516-3

provides a multi-output clock distribution

function with subpicosecond jitter performance, along with an on-

chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to

2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz

can be used.

The AD9516-3 emphasizes low jitter and phase noise to

maximize data converter performance, and it can benefit other

applications with demanding phase noise and jitter requirements.

FUNCTIONAL BLOCK DIAGRAM

REFIN

REF1

REF2

CLK

SWITCHOVER

AND MONITOR

PLL

DIVIDER

AND MUXs

VCO

STATUS

MONITOR

LVPECL

LVDS/CMOS

SERIAL CONTROL PORT

AND

DIGITAL LOGIC

AD9516-3

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

DIV/Φ

06422-001

Figure 1.

The AD9516-3 features six LVPECL outputs (in three pairs)

and four LVDS outputs (in two pairs). Each LVDS output can

be reconfigured as two CMOS outputs. The LVPECL outputs

operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and

the CMOS outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide

ratio and coarse delay (or phase) to be set. The range of division

for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs

allow a range of divisions up to a maximum of 1024.

The AD9516-3 is available in a 64-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated

by connecting the charge pump supply (VCP) to 5 V. A separate

LVPECL power supply can be from 2.5 V to 3.3 V (nominal).

The AD9516-3 is specified for operation over the standard

industrial range of −40°C to +85°C.

AD9516 is used throughout to refer to all the members of the AD9516 family.

However, when AD9516-3 is used, it refers to that specific member of the

AD9516 family.

Summary of content (80 pages)

PAGE 1
4-Output Clock Generator with Integrated 2.0 GHz VCO AD9516-3 Data Sheet FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.
PAGE 2
AD9516-3 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .................................................................... 16 Applications ....................................................................................... 1 ESD Caution................................................................................ 16 General Description .....................................................
PAGE 3
Data Sheet AD9516-3 REVISION HISTORY 2/13—Rev. B to Rev. C Changes to Register 0x140 to Register 0x143 Default Values; Table 52 ............................................................................................. 56 Changes to Register 0x140 to Register 0x143 Default Values; Table 57 ............................................................................................. 71 Updated Outline Dimensions ........................................................80 1/12—Rev. A to Rev.
PAGE 4
AD9516-3 Data Sheet SPECIFICATIONS Typical is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter VS VS_LVPECL VCP RSET Pin Resistor CPRSET Pin Resistor Min 3.135 2.375 VS 2.7 BYPASS Pin Capacitor Typ 3.3 4.12 5.1 Max 3.465 VS 5.25 10 220 Unit V V V kΩ kΩ nF Test Conditions/Comments 3.
PAGE 5
Data Sheet Parameter CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. CPV ICP vs.
PAGE 6
AD9516-3 Data Sheet CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min Typ 01 01 Input Sensitivity, Differential 1 Unit 2.4 1.6 GHz GHz mV p-p 2 V p-p 1.8 1.8 V V mV p-p kΩ pF 150 Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Max 1.3 1.3 3.9 1.57 150 4.7 2 5.
PAGE 7
Data Sheet AD9516-3 TIMING CHARACTERISTICS Table 5.
PAGE 8
AD9516-3 Data Sheet CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6.
PAGE 9
Data Sheet Parameter CLK = 1 GHz, Output = 50 MHz Divider = 20 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset AD9516-3 Min Typ Max −124 −134 −142 −151 −157 −160 −163 Unit Test Conditions/Comments Input slew rate > 1 V/ns dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter LVPECL ABSOLUTE PHASE NOISE VCO = 2.25 GHz; Output = 2.
PAGE 10
AD9516-3 Data Sheet CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min VCO = 1.97 GHz; LVPECL = 245.76 MHz; PLL LBW = 143 kHz Typ Max 129 303 135 302 179 343 VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 143 kHz VCO = 1.97 GHz; LVPECL = 61.
PAGE 11
Data Sheet AD9516-3 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER Min CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1 CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4 CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16 Typ Max Unit 40 80 215 fs rms fs rms fs rms CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 LVDS OUTPUT ADDITIVE TIME JITTER 245 fs rms CLK = 1.
PAGE 12
AD9516-3 Data Sheet DELAY BLOCK ADDITIVE TIME JITTER Table 13. Parameter DELAY BLOCK ADDITIVE TIME JITTER 1 100 MHz Output Delay (1600 µA, 0x1C) Fine Adj. 000000 Delay (1600 µA, 0x1C) Fine Adj. 101111 Delay (800 µA, 0x1C) Fine Adj. 000000 Delay (800 µA, 0x1C) Fine Adj. 101111 Delay (800 µA, 0x4C) Fine Adj. 000000 Delay (800 µA, 0x4C) Fine Adj. 101111 Delay (400 µA, 0x4C) Fine Adj. 000000 Delay (400 µA, 0x4C) Fine Adj. 101111 Delay (200 µA, 0x1C) Fine Adj. 000000 Delay (200 µA, 0x1C) Fine Adj.
PAGE 13
Data Sheet AD9516-3 PD, RESET, AND SYNC PINS Table 15. Parameter INPUT CHARACTERISTICS Min Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low SYNC TIMING Pulse Width Low 2.0 Typ Max 0.8 110 1 2 Unit Test Conditions/Comments These pins each have a 30 kΩ internal pull-up resistor V V µA µA pF 50 ns 1.
PAGE 14
AD9516-3 Data Sheet POWER DISSIPATION Table 17. Parameter POWER DISSIPATION, CHIP Power-On Default Typ Max Unit Test Conditions/Comments 1.0 1.2 W Full Operation; CMOS Outputs at 225 MHz 1.6 2.2 W Full Operation; LVDS Outputs at 225 MHz 1.6 2.
PAGE 15
Data Sheet AD9516-3 TIMING DIAGRAMS tCLK CLK DIFFERENTIAL 80% tPECL LVDS 06422-060 tCMOS tRL tFL 06422-062 20% tLVDS Figure 4. LVDS Timing, Differential Figure 2. CLK/CLK to Clock Output Timing, DIV = 1 DIFFERENTIAL SINGLE-ENDED 80% 80% LVPECL CMOS 10pF LOAD 20% tFP tRC tFC Figure 5. CMOS Timing, Single-Ended, 10 pF Load Figure 3. LVPECL Timing, Differential Rev.
PAGE 16
AD9516-3 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 18. Parameter VS, VS_LVPECL to GND VCP to GND REFIN, REFIN to GND REFIN to REFIN RSET to GND CPRSET to GND CLK, CLK to GND CLK to CLK SCLK, SDIO, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, OUT9, OUT9 to GND SYNC to GND REFMON, STATUS, LD to GND Junction Temperature1 Storage Temperature Range Lead Temperature (10 sec) 1 Rating −0.3 V to +3.6 V −0.3 V to+5.8 V −0.3 V to VS + 0.
PAGE 17
Data Sheet AD9516-3 PIN 1 INDICATOR AD9516-3 TOP VIEW (Not to Scale) LVPECL LVPECL LVDS/CMOS w/FINE DELAY ADJUST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LVDS/CMOS w/FINE DELAY ADJUST LVPECL LVPECL VS REFMON LD VCP CP STATUS REF_SEL SYNC LF BYPASS VS VS CLK CLK NC SCLK LVPECL LVPECL 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 REFIN (REF1) REFIN (REF2) CPRSET VS VS GND RSET VS OUT0 OUT0 VS_LVPECL OUT1 OUT1 VS VS VS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 3
PAGE 18
AD9516-3 Data Sheet Input/ Output N/A I I Pin Type NC 3.3 V CMOS 3.3 V CMOS Mnemonic NC SCLK CS 21 22 23 24 27, 41, 54 37, 44, 59, EPAD 56 55 53 52 43 42 40 39 25 26 28 29 48 O I/O I I I N/A 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.
PAGE 19
Data Sheet AD9516-3 TYPICAL PERFORMANCE CHARACTERISTICS 300 70 3 CHANNELS—6 LVPECL 280 65 260 60 55 KVCO (MHz/V) 220 200 3 CHANNELS—3 LVPECL 180 50 45 40 160 2 CHANNELS—2 LVPECL 35 140 30 120 1 CHANNEL—1 LVPECL 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) 25 1.7 06422-007 100 1.8 Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs 2.0 2.1 2.2 2.3 Figure 10. VCO KVCO vs. Frequency 5.0 180 4.
PAGE 20
Data Sheet –140 10 –145 –10 RELATIVE POWER (dB) 0 –150 –155 –160 –20 –30 –40 –50 –60 –70 –80 –90 –165 –170 0.1 1 10 100 –110 PFD FREQUENCY (MHz) CENTER 122.88MHz 5MHz/DIV SPAN 50MHz 06422-137 –100 06422-013 PFD PHASE NOISE REFERRED TO PFD INPUT (dBc/Hz) AD9516-3 Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; FVCO = 2.21 GHz Figure 13. PFD Phase Noise Referred to PFD Input vs.
PAGE 21
Data Sheet AD9516-3 0.4 0.6 DIFFERENTIAL OUTPUT (V) DIFFERENTIAL OUTPUT (V) 1.0 0.2 –0.2 0.2 0 –0.2 –0.6 5 10 15 20 25 TIME (ns) –0.4 0 1 06422-017 0 06422-014 –1.0 2 TIME (ns) Figure 19. LVPECL Output (Differential) at 100 MHz Figure 22. LVDS Output (Differential) at 800 MHz 1.0 DIFFERENTIAL OUTPUT (V) DIFFERENTIAL OUTPUT (V) 2.8 0.6 0.2 –0.2 1.8 0.8 1 0 2 TIME (ns) 06422-015 –0.2 –1.0 0 20 40 60 80 100 TIME (ns) 06422-018 –0.6 Figure 23.
PAGE 22
AD9516-3 Data Sheet 1600 –80 1400 PHASE NOISE (dBc/Hz) DIFFERENTIAL SWING (mV p-p) –90 1200 1000 –100 –110 –120 –130 0 1 2 3 FREQUENCY (GHz) –150 10k 06422-020 800 Figure 25. LVPECL Differential Swing vs. Frequency Using a Differential Probe Across the Output Pair 100k 1M 10M 100M FREQUENCY (Hz) 06422-023 –140 Figure 28.
PAGE 23
Data Sheet AD9516-3 –120 –110 –125 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –120 –130 –135 –140 –145 –150 –130 –140 –150 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) –160 10 06422-026 –120 –110 PHASE NOISE (dBc/Hz) 1k 10k 100k 1M 10M 100M 10M 100M –120 –130 –150 10 06422-027 100 FREQUENCY (Hz) 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 35. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2 Figure 32.
PAGE 24
AD9516-3 Data Sheet –100 –120 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –110 –120 –130 –140 –130 –140 –150 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) –160 1k 06422-132 –160 10 Figure 37. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4 10k 100k 1M 10M FREQUENCY (Hz) 100M 06422-140 –150 Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.
PAGE 25
Data Sheet AD9516-3 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.
PAGE 26
AD9516-3 Data Sheet DETAILED BLOCK DIAGRAM REF_ SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS REF2 R DIVIDER STATUS REFIN (REF1) PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS PLL REFERENCE LOCK DETECT LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY 1 TO 32 PD SYNC OUT0
PAGE 27
Data Sheet AD9516-3 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS Table 21. Default Settings of Some PLL Registers The AD9516 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 52 and Table 53 through Table 62). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers.
PAGE 28
AD9516-3 Data Sheet REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS REF2 R DIVIDER STATUS REFIN (REF1) PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS PLL REFERENCE LOCK DETECT LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY 1 TO 32 PD SYNC OUT0 LVPECL OUT1 DIGITAL LOG
PAGE 29
Data Sheet AD9516-3 REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS REF2 R DIVIDER STATUS REFIN (REF1) PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS PLL REFERENCE LOCK DETECT LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 OUT0 0 DIVIDE BY 1 TO 32 PD SYNC OUT0 LVPECL OUT1 DIGITAL LOG
PAGE 30
AD9516-3 Data Sheet REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS REF2 R DIVIDER STATUS REFIN (REF1) PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS PLL REFERENCE LOCK DETECT LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY 1 TO 32 PD SYNC OUT0 LVPECL OUT1 DIGITAL LOG
PAGE 31
Data Sheet AD9516-3 Clock Distribution or External VCO < 1600 MHz When the external clock source to be distributed or the external VCO/VCXO is less than 1600 MHz, a configuration that bypasses the VCO divider can be used. This configuration differs from the High Frequency Clock Distribution—CLK or External VCO > 1600 MHz section only in that the VCO divider (divide-by-2, divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is bypassed.
PAGE 32
AD9516-3 Data Sheet Phase-Locked Loop (PLL) REF_SEL VS GND RSET REFMON CPRSET VCP DIST REF REFERENCE SWITCHOVER LD LOCK DETECT REF1 STATUS REF2 PROGRAMMABLE R DELAY R DIVIDER PLL REF STATUS HOLD REFIN (REF1) REFIN (REF2) BYPASS PHASE FREQUENCY DETECTOR N DIVIDER LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS CHARGE PUMP CP PROGRAMMABLE N DELAY VCO STATUS LF STATUS VCO DIVIDE BY 2, 3, 4, 5, OR 6 CLK 0 1 06422-064 1 CLK 0 Figure 46.
PAGE 33
Data Sheet AD9516-3 Charge Pump (CP) AD9516-3 VCO LF 31pF R2 CP R1 CHARGE PUMP BYPASS C1 Figure 47. Example of External Loop Filter for a PLL Using the Internal VCO When using an external VCO, the external loop filter should be referenced to ground. See Figure 48 for an example of an external loop filter for a PLL using an external VCO. AD9516-3 EXTERNAL VCO/VCXO CLK/CLK R2 CP The on-chip VCO is powered by an on-chip, low dropout (LDO), linear voltage regulator.
PAGE 34
AD9516-3 Data Sheet In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible to dc couple to these inputs. If the differential REFIN is driven by a single-ended signal, the unused side (REFIN) should be decoupled via a suitable capacitor to a quiet ground. Figure 49 shows the equivalent circuit of REFIN. VS Automatic revertive switchover relies on the REFMON pin to indicate when REF1 disappears.
PAGE 35
Data Sheet AD9516-3 By using combinations of DM and FD modes, the AD9516 can achieve values of N all the way down to N = 1 and up to N = 26,2175. Table 28 shows how a 10 MHz reference input can be locked to any integer multiple of N. Note that the same value of N can be derived in different ways, as illustrated by the case of N = 12. The user can choose a fixed divide mode of P = 2 with B = 6; use the dual modulus mode of 2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with A = 0, B = 3.
PAGE 36
AD9516-3 Data Sheet By selecting the proper output through the mux on each pin, the DLD function can be made available at the LD, STATUS, and REFMON pins. The DLD circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value (the lock threshold). The loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold).
PAGE 37
Data Sheet AD9516-3 Holdover Automatic/Internal Holdover Mode The AD9516 PLL has a holdover function. Holdover is implemented by putting the charge pump into a state of high impedance. This is useful when the PLL reference clock is lost. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. Without this function, the charge pump is placed into a constant pump-up or pump-down state resulting in a massive VCO frequency shift.
PAGE 38
AD9516-3 Data Sheet The holdover function senses the logic level of the LD pin as a condition to enter holdover. The signal at LD can be from the DLD, ALD, or current source LD mode. It is possible to disable the LD comparator (Register 0x01D[3]), which causes the holdover function to always sense LD as high. If DLD is used, it is possible for the DLD signal to chatter some while the PLL is reacquiring lock. The holdover function may retrigger, thereby preventing the holdover mode from ever terminating.
PAGE 39
Data Sheet AD9516-3 REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 PLL REFERENCE REF2 LOCK DETECT STATUS R DIVIDER PROGRAMMABLE R DELAY STATUS REFIN (REF1) REFIN (REF2) N DIVIDER BYPASS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS LF PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP VCO STATUS VCO STATUS 0 DIVIDE BY 2, 3, 4, 5, OR 6 CLK 1 1 06422-070 CLK 0 Figure 54.
PAGE 40
AD9516-3 Data Sheet VCO calibration must be manually initiated. This allows for flexibility in deciding what order to program registers and when to initiate a calibration, instead of having it happen every time certain PLL registers have their values change.
PAGE 41
Data Sheet AD9516-3 To connect the LVPECL outputs directly to the internal VCO or CLK, the VCO divider must be selected as the source to the distribution section, even if no channel uses it. Either the internal VCO or the CLK can be selected as the source for the direct to output routing. Table 31.
PAGE 42
AD9516-3 Data Sheet Duty Cycle and Duty-Cycle Correction (0, 1, and 2) Table 36. Duty Cycle with VCO Divider, Input Duty Cycle Is X% The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: VCO Divider • • • • Even What are the M and N values for the channel? Is the DCC enabled? Is the VCO divider used? What is the CLK input duty cycle? (The internal VCO has a 50% duty cycle.
PAGE 43
Data Sheet AD9516-3 Phase Offset or Coarse Time Delay (0, 1, and 2) Channel Dividers—LVDS/CMOS Outputs Each channel divider allows for a phase offset, or a coarse time delay, to be programmed by setting register bits (see Table 38). These settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset or delay the rising edge of the output of the divider. This delay is with respect to a nondelayed output (that is, with a phase offset of zero).
PAGE 44
AD9516-3 Data Sheet Duty Cycle and Duty-Cycle Correction (Divider 3 and Divider 4) The same duty cycle and DCC considerations apply to Divider 3 and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see the Duty Cycle and Duty-Cycle Correction (0, 1, and 2) section); however, with these channel dividers, the number of possible configurations is even more complex. Duty-cycle correction on Divider 3 and Divider 4 requires the following channel divider conditions: • • • • An even DX.Y must be set as MX.
PAGE 45
Data Sheet AD9516-3 Table 44. Divider 3, Divider 4 Duty Cycle; VCO Divider Not Used; Duty Cycle Correction On (DCCOFF = 0) X% X% 50% X% 50% X% 50% X% 50% X% DX.1 DX.2 NX.1 + MX.1 + 2 1 Even (NX.1 = MX.1) 1 Even (NX.1 = MX.1) Odd (MX.1 = NX.1 + 1) Odd (MX.1 = NX.1 + 1) Odd (MX.1 = NX.1 + 1) Even (NX.1 = MX.1) Even (NX.1 = MX.1) Odd (MX.1 = NX.1 + 1) Odd (MX.1 = NX.1 + 1) Odd (MX.1 = NX.1 + 1) Odd (MX.1 = NX.1 + 1) NX.2 + MX.
PAGE 46
AD9516-3 Data Sheet Calculating the Fine Delay Synchronization of the outputs is executed in several ways, as follows: The following values and equations are used to calculate the delay of the delay block. • IRAMP (µA) = 200 × (Ramp Current + 1) • Number of Capacitors = Number of Bits = 0 in Ramp Capacitors + 1 Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1. • Delay Range (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) × 1.3286  No.
PAGE 47
Data Sheet AD9516-3 CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC INPUT TO VCO DIVIDER 1 1 INPUT TO CHANNEL DIVIDER 2 3 4 5 6 7 8 9 10 11 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 06422-073 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT Figure 57.
PAGE 48
AD9516-3 Data Sheet LVPECL Outputs—OUT0 to OUT5 3.5mA The LVPECL differential voltage (VOD) is selectable from ~400 mV to ~960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]). The LVPECL outputs have dedicated pins for power supply (VS_LVPECL), allowing a separate power supply to be used. VS_LVPECL can be from 2.5 V to 3.3 V.
PAGE 49
Data Sheet AD9516-3 POWER-DOWN MODES In asynchronous power-down mode, the device powers down as soon as the registers are updated. Chip Power-Down via PD The AD9516 can be put into a power-down condition by pulling the PD pin low. Power-down turns off most of the functions and currents inside the AD9516. The chip remains in this power-down state until PD is brought back to logic high.
PAGE 50
AD9516-3 Data Sheet SERIAL CONTROL PORT The AD9516 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9516 serial control port is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR® protocols. The serial control port allows read/write access to all registers that configure the AD9516.
PAGE 51
Data Sheet AD9516-3 Read If the instruction word is for a read operation, the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 3 as determined by [W1:W0]. If N = 4, the read operation is in streaming mode, continuing until CS is raised. Streaming mode does not skip over reserved or blank registers. The readback data is valid on the falling edge of SCLK. The default mode of the AD9516 serial control port is the bidirectional mode.
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AD9516-3 Data Sheet Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 06422-038 DON'T CARE Figure 64.
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Data Sheet AD9516-3 tS tC CS tCLK tHI SCLK tLO tDS SDIO BIT N BIT N + 1 Figure 69. Serial Control Port Timing—Write Table 50.
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AD9516-3 Data Sheet THERMAL PERFORMANCE Table 51. Thermal Parameters for the 64-Lead LFCSP Symbol θJA θJMA θJMA ΨJB θJC ΨJT Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Junction-to-ambient thermal resistance, natural convection per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
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Data Sheet AD9516-3 REGISTER MAP OVERVIEW Table 52. Register Map Overview Reg. Addr.
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AD9516-3 Data Sheet Reg. Addr.
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Data Sheet AD9516-3 Reg. Addr.
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AD9516-3 Reg. Addr. (Hex) Parameter System Power-down 0x230 and sync 0x231 Update All Registers Update all 0x232 registers Data Sheet Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Powerdown sync Powerdown distribution reference Reserved Reserved Blank Blank Rev.
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Data Sheet AD9516-3 REGISTER MAP DESCRIPTIONS Table 53 through Table 62 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2]. Table 53. Serial Port Configuration Reg.
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AD9516-3 Data Sheet Table 54. PLL Reg. Addr.
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Data Sheet Reg. Addr. (Hex) 0x016 0x017 Bits [2:0] [7:2] Name Prescaler P STATUS pin control AD9516-3 Description Prescaler: DM = dual modulus, and FD = fixed divide. 2 1 0 Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 (2/3 mode). 0 1 1 DM Divide-by-4 (4/5 mode). 1 0 0 DM Divide-by-8 (8/9 mode). 1 0 1 DM Divide-by-16 (16/17 mode). 1 1 0 DM Divide-by-32 (32/33 mode) (default). 1 1 1 FD Divide-by-3. Selects the signal that is connected to the STATUS pin.
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AD9516-3 Data Sheet Reg. Addr. (Hex) 0x017 Bits [1:0] Name Antibacklash pulse width 0x018 [6:5] Lock detect counter 4 Digital lock detect window 3 Disable digital lock detect [2:1] VCO cal divider [0] VCO cal now 0x019 [7:6] R, A, B counters SYNC pin reset 0x01A [5:3] [2:0] [6] R path delay N path delay Reference frequency monitor threshold Description 1 0 Antibacklash Pulse Width (ns) 0 0 2.9 (default). 0 1 1.3. 1 0 6.0. 1 1 2.9.
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Data Sheet Reg. Addr. (Hex) 0x01A Bits [5:0] Name LD pin control 0x01B 7 VCO frequency monitor 6 REF2 (REFIN) frequency monitor 5 REF1 (REFIN) frequency monitor AD9516-3 Description Selects the signal that is connected to the LD pin. Level or Dynamic Signal Signal at LD Pin 5 4 3 2 1 0 0 0 0 0 0 0 LVL Digital lock detect (high = lock, low = unlock) (default). 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect).
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AD9516-3 Data Sheet Reg. Addr. (Hex) 0x01B Bits [4:0] Name REFMON pin control 0x01C 7 6 Disable switchover deglitch Select REF2 5 Use REF_SEL pin 4 3 2 Reserved Reserved REF2 power-on 1 REF1 power-on 0 Differential reference Description Selects the signal that is connected to the REFMON pin. Level or Dynamic Signal Signal at REFMON Pin 4 3 2 1 0 0 0 0 0 0 LVL Ground (dc) (default). 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode).
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Data Sheet Reg. Addr. (Hex) 0x01D 0x01F Bits 4 Name PLL status register disable 3 LD pin comparator enable 2 Holdover enable 1 External holdover control 0 Holdover enable 6 VCO cal finished 5 Holdover active 4 REF2 selected 3 VCO frequency > threshold 2 REF2 frequency > threshold 1 REF1 frequency > threshold 0 Digital lock detect AD9516-3 Description Disables the PLL status register readback. 0: PLL status register enable (default). 1: PLL status register disable.
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AD9516-3 Data Sheet Table 55. Fine Delay Adjust—OUT6 to OUT9 Reg. Addr. (Hex) 0x0A0 Bits 0 Name OUT6 delay bypass 0x0A1 [5:3] OUT6 ramp capacitors [2:0] OUT6 ramp current 0x0A2 [5:0] OUT6 delay fraction 0x0A3 0 OUT7 delay bypass 0x0A4 [5:3] OUT7 ramp capacitors Description Bypasses or uses the delay function. 0: uses delay function. 1: bypasses delay function (default). Selects the number of ramp capacitors used by the delay function.
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Data Sheet Reg. Addr. (Hex) 0x0A4 Bits [2:0] Name OUT7 ramp current 0x0A5 [5:0] OUT7 delay fraction 0x0A6 0 OUT8 delay bypass 0x0A7 [5:3] OUT8 ramp capacitors [2:0] OUT8 ramp current [5:0] OUT8 delay fraction 0x0A8 AD9516-3 Description Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale.
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AD9516-3 Data Sheet Reg. Addr. (Hex) 0x0A9 Bits 0 Name OUT9 delay bypass 0x0AA [5:3] OUT9 ramp capacitors [2:0] OUT9 ramp current [5:0] OUT9 delay fraction 0x0AB Description Bypasses or uses the delay function. 0: uses delay function. 1: bypasses delay function (default). Selects the number of ramp capacitors used by the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale.
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Data Sheet Reg. Addr. (Hex) 0x0F1 0x0F2 0x0F3 Bits 4 Name OUT1 invert [3:2] OUT1 LVPECL differential voltage [1:0] OUT1 power-down 4 OUT2 invert [3:2] OUT2 LVPECL differential voltage [1:0] OUT2 power-down 4 OUT3 invert [3:2] OUT3 LVPECL differential voltage [1:0] OUT3 power-down AD9516-3 Description Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (VOD).
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AD9516-3 Reg. Addr. (Hex) 0x0F4 0x0F5 Data Sheet Bits 4 Name OUT4 invert [3:2] OUT4 LVPECL differential voltage [1:0] OUT4 power-down 4 OUT5 invert [3:2] OUT5 LVPECL differential voltage [1:0] OUT5 power-down Description Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 LVPECL power-down modes. 1 0 Mode 0 0 Normal operation (default).
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Data Sheet AD9516-3 Table 57. LVDS/CMOS Outputs Reg. Addr. (Hex) 0x140 0x141 Bits [7:5] Name OUT6 output polarity 4 OUT6 CMOS B 3 OUT6 select LVDS/CMOS [2:1] OUT6 LVDS output current 0 OUT6 power-down [7:5] OUT7 output polarity 4 OUT7 CMOS B 3 OUT7 select LVDS/CMOS [2:1] OUT7 LVDS output current Description In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity.
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AD9516-3 Data Sheet Reg. Addr. (Hex) 0x141 Bits 0 Name OUT7 power-down 0x142 [7:5] OUT8 output polarity 4 OUT8 CMOS B 3 OUT8 select LVDS/CMOS [2:1] OUT8 LVDS output current 0 OUT8 power-down [7:5] OUT9 output polarity 4 OUT9 CMOS B 3 OUT9 select LVDS/CMOS 0x143 Description Power-down output (LVDS/CMOS). 0: power on. 1: power off (default). In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity.
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Data Sheet Reg. Addr. (Hex) 0x143 Bits [2:1] Name OUT9 LVDS output current 0 OUT9 power-down AD9516-3 Description Sets output current level in LVDS mode. This has no effect in CMOS mode. 2 1 Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 Power-down output (LVDS/CMOS). 0: power on. 1: power off (default). Table 58. LVPECL Channel Dividers Reg. Addr.
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AD9516-3 Data Sheet Reg. Addr. (Hex) 0x194 Bits 4 Name Divider 1 start high 0x195 [3:0] 1 Divider 1 phase offset Divider 1 direct to output 0 Divider 1 DCCOFF [7:4] Divider 2 low cycles [3:0] Divider 2 high cycles 7 Divider 2 bypass 6 Divider 2 nosync 5 Divider 2 force high 4 Divider 2 start high [3:0] 1 Divider 2 phase offset Divider 2 direct to output 0 Divider 2 DCCOFF 0x196 0x197 0x198 Description Selects clock output to start high or start low. 0: starts low (default).
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Data Sheet Reg. Addr. (Hex) 0x19C Bits 5 Name Bypass Divider 3.2 4 Bypass Divider 3.1 3 Divider 3 nosync 2 Divider 3 force high 1 Start High Divider 3.2 0 Start High Divider 3.1 0x19D 0 Divider 3 DCCOFF 0x19E [7:4] Low Cycles Divider 4.1 [3:0] High Cycles Divider 4.1 [7:4] [3:0] [7:4] Phase Offset Divider 4.2 Phase Offset Divider 4.1 Low Cycles Divider 4.2 [3:0] High Cycles Divider 4.2 5 Bypass Divider 4.2 4 Bypass Divider 4.
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AD9516-3 Data Sheet Table 60. VCO Divider and CLK Input Reg. Addr (Hex) 0x1E0 Bits [2:0] Name VCO divider 0x1E1 4 Power down clock input section 3 Power down VCO clock interface 2 Power down VCO and CLK 1 Select VCO or CLK 0 Bypass VCO divider 0x1E1 Description 2 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 Divide 2. 3. 4 (default). 5. 6. Output static. Note that setting the VCO divider static should occur only after VCO calibration. 1 1 0 Output static.
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Data Sheet AD9516-3 APPLICATIONS INFORMATION Within the AD9516 family, lower VCO frequencies generally result in slightly lower jitter. The difference in integrated jitter (from 12 kHz to 20 MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.45 GHz to 2.95 GHz) of the AD9516 family.
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AD9516-3 Data Sheet LVPECL CLOCK DISTRIBUTION The LVPECL outputs of the AD9516 provide the lowest jitter clock signals that are available from the AD9516. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 59 shows the LVPECL output stage. In most applications, an LVPECL far-end Thevenin termination (see Figure 71) or Y-termination (see Figure 72) is recommended.
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Data Sheet AD9516-3 The AD9516 provides four clock outputs (OUT6 to OUT9) that are selectable as either CMOS or LVDS level outputs. When selected as CMOS, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as noninverting or inverting. These outputs are 3.3 V CMOS compatible. Whenever single-ended CMOS clocking is used, some of the following general guidelines should be used.
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AD9516-3 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.25 0.18 0.60 MAX 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 16 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-12-2012-C 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.