Datasheet

AD9516-3 Data Sheet
Rev. C | Page 14 of 80
POWER DISSIPATION
Table 17.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER DISSIPATION, CHIP
Power-On Default 1.0 1.2 W No clock; no programming; default register values;
does not include power dissipated in external resistors
Full Operation; CMOS Outputs at 225 MHz 1.6 2.2 W PLL on; internal VCO = 2250 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 562.5 MHz;
eight CMOS outputs (10 pF load) at 225 MHz; all fine delay on,
maximum current; does not include power dissipated in
external resistors
Full Operation; LVDS Outputs at 225 MHz 1.6 2.3 W PLL on; internal VCO = 2250 MHz, VCO divider = 2;
all channel dividers on; six LVPECL outputs at 562.5 MHz;
four LVDS outputs at 225 MHz; all fine delay on, maximum
current; does not include power dissipated in external
resistors
PD
Power-Down
75 185 mW PD
pin pulled low; does not include power dissipated
in terminations
PD
Power-Down, Maximum Sleep
31 mW PD
pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;
SYNC power-down, Register 0x230[2] = 1b; REF for distribution
power-down, Register 0x230[1] = 1b
VCP Supply 4 4.8 mW PLL operating; typical closed loop configuration
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power delta when a function is enabled/disabled
VCO Divider 30 mW VCO divider bypassed
REFIN (Differential) 20 mW All references off to differential reference enabled
REF1, REF2 (Single-Ended) 4 mW All references off to REF1 or REF2 enabled; differential
reference not enabled
VCO 70 mW CLK input selected to VCO selected
PLL 75 mW PLL off to PLL on, normal operation; no reference enabled
Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32
LVPECL Channel (Divider Plus Output Driver) 160 mW No LVPECL output on to one LVPECL output on,
independent of frequency
LVPECL Driver 90 mW Second LVPECL output turned on, same channel
LVDS Channel (Divider Plus Output Driver)
120
mW
No LVDS output on to one LVDS output on; see Figure 8 for
dependence on output frequency
LVDS Driver 50 mW Second LVDS output turned on, same channel
CMOS Channel (Divider Plus Output Driver) 100 mW Static; no CMOS output on to one CMOS output on;
see Figure 9 for variation over output frequency
CMOS Driver (Second in Pair)
0
mW
Static; second CMOS output, same pair, turned on
CMOS Driver (First in Second Pair) 30 mW Static; first output, second pair, turned on
Fine Delay Block 50 mW Delay block off to delay block enabled; maximum current
setting