Datasheet

AD9516-3 Data Sheet
Rev. C | Page 30 of 80
PROGRAMMABLE
N DELAY
REFIN (REF1)
REFIN (REF2)
CLK
CLK
REF1
REF2
AD9516-3
STATUS
STATUS
R
DIVIDER
VCO STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_SEL CPRSET
V
CP
V
S GND RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
VCO
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PLL
REFERENCE
HOLD
OUT0
OUT1
OUT0
OUT1
LVPECL
DIVIDE BY
1 TO 32
OUT2
OUT3
OUT2
OUT3
LVPECL
DIVIDE BY
1 TO 32
OUT4
OUT5
OUT4
OUT5
LVPECL
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
OUT6 (OUT6A)
OUT6 (OUT6B)
∆ t
OUT7 (OUT7A)
OUT7 (OUT7B)
∆ t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
OUT8 (OUT8A)
OUT8 (OUT8B)
∆ t
OUT9 (OUT9A)
OUT9 (OUT9B)
∆ t
DIVIDE BY
1 TO 32
01
DIVIDE BY
2, 3, 4, 5, OR 6
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
06422-028
Figure 45. Clock Distribution or External VCO < 1600 MHz