Datasheet

Data Sheet AD9516-3
Rev. C | Page 5 of 80
Parameter Min Typ Max Unit Test Conditions/Comments
CHARGE PUMP (CP)
I
CP
Sink/Source Programmable
High Value 4.8 mA With CP
RSET
= 5.1 kΩ
Low Value 0.60 mA
Absolute Accuracy 2.5 % CP
V
= V
CP
/2
CP
RSET
Range 2.7/10 kΩ
I
CP
High Impedance Mode Leakage 1 nA
Sink-and-Source Current Matching
2
%
0.5 < CP
V
< V
CP
− 0.5 V
I
CP
vs. CP
V
1.5 % 0.5 < CP
V
< V
CP
− 0.5 V
I
CP
vs. Temperature 2 % CP
V
= V
CP
/2
PRESCALER (PART OF N DIVIDER)
See the
VCXO/VCO Feedback Divider N—P, A, B, R section
Prescaler Input Frequency
P = 1 FD
300
MHz
P = 2 FD 600 MHz
P = 3 FD 900 MHz
P = 2 DM (2/3)
200
MHz
P = 4 DM (4/5) 1000 MHz
P = 8 DM (8/9) 2400 MHz
P = 16 DM (16/17) 3000 MHz
P = 32 DM (32/33) 3000 MHz
Prescaler Output Frequency
300
MHz
A, B counter input frequency (prescaler input frequency divided
by P)
PLL DIVIDER DELAYS Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 54
000 Off ps
001 330 ps
010 440 ps
011 550 ps
100 660 ps
101 770 ps
110
880
ps
111 990 ps
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
The PLL in-band phase noise floor is estimated by measuring the
in-band phase noise at the output of the VCO and subtracting
20log(N) (where N is the value of the N divider)
At 500 kHz PFD Frequency −165 dBc/Hz
At 1 MHz PFD Frequency −162 dBc/Hz
At 10 MHz PFD Frequency −151 dBc/Hz
At 50 MHz PFD Frequency
−143
dBc/Hz
PLL Figure of Merit (FOM) −220 dBc/Hz Reference slew rate > 0.25 V/ns; FOM + 10log (f
PFD
) is an approxi-
mation of the PFD/CP in-band phase noise (in the flat region)
inside the PLL loop bandwidth; when running closed loop, the
phase noise, as observed at the VCO output, is increased by 20log(N)
PLL DIGITAL LOCK DETECT WINDOW
2
Signal available at LD, STATUS, and REFMON pins when selected
by appropriate register settings
Required to Lock (Coincidence of Edges) Selected by Register 0x017[1:0] and Register 0x018[4]
Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b
High Range (ABP 1.3 ns, 2.9 ns)
7.5
ns
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
High Range (ABP 6.0 ns) 3.5 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
To Unlock After Lock (Hysteresis)
2
Low Range (ABP 1.3 ns, 2.9 ns) 7 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
High Range (ABP 1.3 ns, 2.9 ns)
15
ns
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
High Range (ABP 6.0 ns) 11 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
1
REFIN and
REFIN
self-bias points are offset slightly to avoid chatter on an open input condition.
2
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.