Datasheet

AD9516-3 Data Sheet
Rev. C | Page 76 of 80
Table 60. VCO Divider and CLK Input
Reg.
Addr
(Hex)
Bits Name Description
0x1E0
[2:0]
VCO divider
2
1
0
Divide
0 0 0 2.
0
0
1
3.
0 1 0 4 (default).
0 1 1 5.
1 0 0 6.
1 0 1 Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
1 1 0 Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
1 1 1 Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
0x1E1 4 Power down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
3 Power down VCO clock interface Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
2 Power down VCO and CLK Powers down both VCO and CLK input.
0; normal operation (default).
1: power-down.
0x1E1 1 Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
0 Bypass VCO divider Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
Table 61. System
Reg.
Addr.
(Hex) Bits Name Description
0x230 2 Power down SYNC Powers down the SYNC function.
0: normal operation of the SYNC function (default).
1: powers down SYNC circuitry.
1 Power down distribution reference Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
0 Soft SYNC The soft SYNC bit works the same as the
SYNC
pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
0: same as
SYNC
high (default).
1: same as
SYNC
low.
Table 62. Update All Registers
Reg.
Addr
(Hex) Bits Name Description
0x232 0 Update all registers This bit must be set to 1 to transfer the contents of the buffer registers into the active
registers. This bit is self-clearing; that is, it does not have to be set back to 0.
1 (self-clearing): updates all active registers to the contents of the buffer registers.