2-Output Clock Generator with Integrated 2.0 GHz VCO AD9517-3 Data Sheet FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.
AD9517-3 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution................................................................................ 17 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions........................... 18 General Description ......................................................................
Data Sheet AD9517-3 REVISION HISTORY 3/13—Rev. D to Rev. E Changes to Table 52 ........................................................................ 57 Changes to Table 57 ........................................................................ 70 1/12—Rev. C to Rev. D Changes to Table 62 ........................................................................75 5/11—Rev. B to Rev. C Changes to Features, Applications, and General Description Sections ....................................................
AD9517-3 Data Sheet SPECIFICATIONS Typical is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter VS VS_LVPECL VCP RSET Pin Resistor CPRSET Pin Resistor Min 3.135 2.375 VS 2.7 BYPASS Pin Capacitor Typ 3.3 4.12 5.1 Max 3.465 VS 5.25 10 220 Unit V V V kΩ kΩ nF Test Conditions/Comments 3.
Data Sheet Parameter CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. CPV ICP vs.
AD9517-3 Data Sheet CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min Typ 01 01 Input Sensitivity, Differential 1 Unit 2.4 1.6 GHz GHz mV p-p 2 V p-p 1.8 1.8 V V mV p-p kΩ pF 150 Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Max 1.3 1.3 3.9 1.57 150 4.7 2 5.
Data Sheet Parameter CMOS CLOCK OUTPUTS OUT4A, OUT4B, OUT5A, OUT5B, OUT6A, OUT6B, OUT7A, OUT7B Output Frequency Output Voltage High (VOH) Low (VOL) Source Current Static Dynamic Sink Current Static Dynamic AD9517-3 Min Typ Max Unit Test Conditions/Comments Single-ended; termination = 10 pF 250 MHz See Figure 27 0.1 V V At 1 mA load At 1 mA load Exceeding these values can result in damage to the part 20 16 mA mA 8 16 mA mA VS − 0.
AD9517-3 Data Sheet TIMING CHARACTERISTICS Table 5.
Data Sheet AD9517-3 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6.
AD9517-3 Parameter CLK = 1 GHz, Output = 50 MHz Divider = 20 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 1 MHz Offset >10 MHz Offset Data Sheet Min Typ Max −124 −134 −142 −151 −157 −160 −163 Unit Test Conditions/Comments Input slew rate > 1 V/ns dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter LVPECL ABSOLUTE PHASE NOISE VCO = 2.25 GHz; Output = 2.
Data Sheet AD9517-3 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min VCO = 1.97 GHz; LVPECL = 245.76 MHz; PLL LBW = 143 kHz Typ Max 129 303 135 302 179 343 VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 143 kHz VCO = 1.97 GHz; LVPECL = 61.
AD9517-3 Data Sheet CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER Min CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1 CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4 CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16 Typ Max Unit 40 80 215 fs rms fs rms fs rms CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 LVDS OUTPUT ADDITIVE TIME JITTER 245 fs rms CLK = 1.
Data Sheet AD9517-3 DELAY BLOCK ADDITIVE TIME JITTER Table 13. Parameter DELAY BLOCK ADDITIVE TIME JITTER 1 100 MHz Output Delay (1600 µA, 0x1C) Fine Adj. 000000b Delay (1600 µA, 0x1C) Fine Adj. 101111b Delay (800 µA, 0x1C) Fine Adj. 000000b Delay (800 µA, 0x1C) Fine Adj. 101111b Delay (800 µA, 0x4C) Fine Adj. 000000b Delay (800 µA, 0x4C) Fine Adj. 101111b Delay (400 µA, 0x4C) Fine Adj. 000000b Delay (400 µA, 0x4C) Fine Adj. 101111b Delay (200 µA, 0x1C) Fine Adj. 000000b Delay (200 µA, 0x1C) Fine Adj.
AD9517-3 Data Sheet PD, SYNC, AND RESET PINS Table 15. Parameter INPUT CHARACTERISTICS Min Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low SYNC TIMING Pulse Width Low 2.0 Typ Max 0.8 1 110 2 Unit Test Conditions/Comments These pins each have a 30 kΩ internal pull-up resistor V V µA µA pF 50 ns 1.
Data Sheet AD9517-3 POWER DISSIPATION Table 17. Parameter POWER DISSIPATION, CHIP Power-On Default Typ Max Unit Test Conditions/Comments 1.0 1.2 W Full Operation; CMOS Outputs at 225 MHz 1.4 2.0 W Full Operation; LVDS Outputs at 225 MHz 1.4 2.
AD9517-3 Data Sheet TIMING DIAGRAMS tCLK CLK DIFFERENTIAL tPECL 80% LVDS tLVDS tCMOS tRL tFL 06427-062 06427-060 20% Figure 4. LVDS Timing, Differential Figure 2. CLK/CLK to Clock Output Timing, DIV = 1 DIFFERENTIAL SINGLE-ENDED 80% 80% LVPECL CMOS 10pF LOAD 20% tFP tRC tFC Figure 5. CMOS Timing, Single-Ended, 10 pF Load Figure 3. LVPECL Timing, Differential Rev.
Data Sheet AD9517-3 ABSOLUTE MAXIMUM RATINGS Table 18. Parameter VS, VS_LVPECL to GND VCP to GND REFIN, REFIN to GND REFIN to REFIN RSET to GND CPRSET to GND CLK, CLK to GND CLK to CLK SCLK, SDIO, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3,OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7 to GND SYNC to GND REFMON, STATUS, LD to GND Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec) 1 Rating −0.3 V to +3.6 V −0.3 V to +5.8 V −0.3 V to VS + 0.3 V −3.3 V to +3.
AD9517-3 Data Sheet 1 37 39 38 40 41 42 44 45 46 43 36 PIN 1 INDICATOR 2 VS 35 OUT4 (OUT4A) 3 34 OUT4 (OUT4B) 4 33 OUT5 (OUT5A) 32 OUT5 (OUT5B) 5 6 AD9517-3 31 VS 7 TOP VIEW (Not to Scale) 30 VS 29 OUT7 (OUT7B) 24 23 22 21 20 19 VS SCLK CS SDO SDIO RESET PD OUT2 OUT2 VS_LVPECL OUT3 OUT3 VS 18 25 17 26 OUT6 (OUT6A) 12 16 27 OUT6 (OUT6B) 11 15 28 OUT7 (OUT7A) 10 14 9 06427-003 8 13 REFMON LD VCP CP STATUS REF_SEL SYNC LF BYPASS VS CLK CLK 47 48 REFIN (REF
Data Sheet Pin No. 15 16 Input/ Output O I/O 17 18 21, 40 42 41 39 38 19 20 22 23 35 I I I O O O O O O O O O 34 O 33 O 32 O 26 O 27 O 28 O 29 O 44 O 46 O 47 I 48 I EPAD AD9517-3 Pin Type 3.3 V CMOS 3.3 V CMOS Mnemonic SDO SDIO RSET Description Serial Control Port. Unidirectional serial data output. Serial Control Port. Bidirectional serial data input/output and unidirectional serial data input. Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.
AD9517-3 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 240 70 2 CHANNELS—4 LVPECL 65 220 60 55 KVCO (MHz/V) CURRENT (mA) 200 180 2 CHANNELS—2 LVPECL 160 50 45 40 140 35 1 CHANNEL—1 LVPECL 120 0 1000 500 1500 2500 2000 3000 FREQUENCY (MHz) 25 1.7 06427-007 100 1.8 Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs 2.0 2.1 2.3 2.2 Figure 10. VCO KVCO vs. Frequency 180 5.0 4.5 2 CHANNELS—4 LVDS CURRENT FROM CP PIN (mA) 160 CURRENT (mA) 1.
AD9517-3 –140 10 –145 –10 RELATIVE POWER (dB) 0 –150 –155 –160 –20 –30 –40 –50 –60 –70 –80 –90 –165 –170 0.1 1 10 100 –110 PFD FREQUENCY (MHz) CENTER 122.88MHz 5MHz/DIV SPAN 50MHz 06427-137 –100 06427-013 PFD PHASE NOISE REFERRED TO PFD INPUT (dBc/Hz) Data Sheet Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; fVCO = 2.21 GHz Figure 13. PFD Phase Noise Referred to PFD Input vs.
AD9517-3 Data Sheet 0.4 0.6 DIFFERENTIAL OUTPUT (V) DIFFERENTIAL OUTPUT (V) 1.0 0.2 –0.2 0.2 0 –0.2 –0.6 5 15 10 20 25 TIME (ns) –0.4 1 0 06427-017 0 06427-014 –1.0 2 TIME (ns) Figure 19. LVPECL Output (Differential) at 100 MHz Figure 22. LVDS Output (Differential) at 800 MHz 1.0 OUTPUT (V) DIFFERENTIAL OUTPUT (V) 2.8 0.6 0.2 –0.2 1.8 0.8 0 1 2 TIME (ns) 06427-015 –0.2 –1.0 0 20 40 60 80 100 TIME (ns) Figure 20.
Data Sheet AD9517-3 1600 –80 1400 PHASE NOISE (dBc/Hz) DIFFERENTIAL SWING (mV p-p) –90 1200 1000 –100 –110 –120 –130 0 2 1 3 FREQUENCY (GHz) –150 10k 06427-020 800 Figure 25. LVPECL Differential Swing vs. Frequency Using a Differential Probe Across the Output Pair 100k 1M 10M 100M FREQUENCY (Hz) 06427-023 –140 Figure 28.
AD9517-3 Data Sheet –120 –110 –125 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –120 –130 –135 –140 –145 –150 –130 –140 –150 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) –160 10 06427-026 –120 –110 PHASE NOISE (dBc/Hz) 1k 10k 100k 1M 10M 100M 10M 100M –120 –130 –150 10 06427-027 100 FREQUENCY (Hz) 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 35. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2 Figure 32.
Data Sheet AD9517-3 –100 –120 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –110 –120 –130 –140 –130 –140 –150 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) –160 1k 06427-132 –160 10 Figure 37. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4 10k 100k 1M 10M 100M FREQUENCY (Hz) 06427-140 –150 Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.
AD9517-3 Data Sheet TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.
Data Sheet AD9517-3 DETAILED BLOCK DIAGRAM REF_ SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS REF2 R DIVIDER STATUS REFIN (REF1) PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS PLL REFERENCE LOCK DETECT LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY 1 TO 32 PD SYNC OUT0
AD9517-3 Data Sheet THEORY OF OPERATION OPERATIONAL CONFIGURATIONS Table 21. Default Settings of Some PLL Registers The AD9517 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 52 and Table 53 through Table 62). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers.
Data Sheet AD9517-3 REF_ SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS REF2 R DIVIDER STATUS REFIN (REF1) PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS PLL REFERENCE LOCK DETECT LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY 1 TO 32 PD SYNC OUT0 LVPECL OUT1 DIGITAL LO
AD9517-3 Data Sheet REF_ SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS REF2 R DIVIDER STATUS REFIN (REF1) PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS PLL REFERENCE LOCK DETECT LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER PROGRAMMABLE N DELAY A/B COUNTERS PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY 1 TO 32 PD SYNC OUT0 LVPECL OUT1 DIGITAL LO
Data Sheet AD9517-3 REF_ SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS REF2 R DIVIDER STATUS REFIN (REF1) PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS PLL REFERENCE LOCK DETECT LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY 1 TO 32 PD SYNC OUT0 LVPECL OUT1 DIGITAL LO
AD9517-3 Data Sheet Clock Distribution or External VCO < 1600 MHz When the external clock source to be distributed or the external VCO/VCXO is less than 1600 MHz, a configuration that bypasses the VCO divider can be used. This configuration differs from the High Frequency Clock Distribution—CLK or External VCO > 1600 MHz section only in that the VCO divider (divide-by-2, divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is bypassed.
Data Sheet AD9517-3 Phase-Locked Loop (PLL) REF_SEL VS GND RSET REFMON CPRSET VCP DIST REF REFERENCE SWITCHOVER LD LOCK DETECT REF1 STATUS REF2 PROGRAMMABLE R DELAY R DIVIDER STATUS PLL REF HOLD REFIN (REF1) REFIN (REF2) BYPASS N DIVIDER LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP VCO STATUS LF STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK 0 1 CLK 1 06427-064 VCO 0 Figure 46.
AD9517-3 Data Sheet The charge pump is controlled by the PFD. The PFD monitors the phase and frequency relationship between its two inputs, and tells the CP to pump up or pump down to charge or discharge the integrating node (part of the loop filter). The integrated and filtered CP current is transformed into a voltage that drives the tuning node of the internal VCO through the LF pin (or the tuning pin of an external VCO) to move the VCO frequency up or down.
Data Sheet AD9517-3 In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible to dc couple to these inputs. If the differential REFIN is driven by a single-ended signal, the unused side (REFIN) should be decoupled via a suitable capacitor to a quiet ground. Figure 49 shows the equivalent circuit of REFIN. VS Automatic revertive switchover relies on the REFMON pin to indicate when REF1 disappears.
AD9517-3 Data Sheet By using combinations of the DM and FD modes, the AD9517 can achieve values of N all the way down to N = 1 and up to N = 26,2175. Table 28 shows how a 10 MHz reference input can be locked to any integer multiple of N. Note that the same value of N can be derived in different ways, as illustrated by the case of N = 12. The user can choose a fixed divide mode of P = 2 with B = 6; use the dual modulus mode of 2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with A = 0, B = 3.
Data Sheet AD9517-3 DIGITAL LOCK DETECT (DLD) By selecting the proper output through the mux on each pin, the DLD function can be made available at the LD, STATUS, and REFMON pins. The DLD circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value (the lock threshold). The loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold).
AD9517-3 Data Sheet Holdover Automatic/Internal Holdover Mode The AD9517 PLL has a holdover function. Holdover is implemented by putting the charge pump into a state of high impedance. This is useful when the PLL reference clock is lost. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. Without this function, the charge pump is placed into a constant pump-up or pump-down state, resulting in a massive VCO frequency shift.
Data Sheet AD9517-3 If DLD is used, it is possible for the DLD signal to chatter some while the PLL is reacquiring lock. The holdover function may retrigger, thereby preventing the holdover mode from ever terminating. Use of the current source lock detect mode is recommended to avoid this situation (see the Current Source Digital Lock Detect section). Once in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present.
AD9517-3 Data Sheet REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS R DIVIDER STATUS REFIN (REF1) PLL REFERENCE REF2 LOCK DETECT PROGRAMMABLE R DELAY REFIN (REF2) BYPASS LOW DROPOUT REGULATOR (LDO) N DIVIDER P, P + 1 PRESCALER A/B COUNTERS LF PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP VCO STATUS VCO STATUS 0 DIVIDE BY 2, 3, 4, 5, OR 6 CLK 1 1 06427-070 CLK 0 Figure 54.
Data Sheet AD9517-3 VCO calibration must be manually initiated. This allows for flexibility in deciding what order to program registers and when to initiate a calibration, instead of having it happen every time certain PLL registers have their values change.
AD9517-3 Data Sheet To connect the LVPECL outputs directly to the internal VCO or CLK, the VCO divider must be selected as the source to the distribution section, even if no channel uses it. Either the internal VCO or the CLK can be selected as the source for the direct-to-output routing. Table 31.
Data Sheet AD9517-3 Duty Cycle and Duty-Cycle Correction (0, 1) The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: • • • • What are the M and N values for the channel? Is the DCC enabled? Is the VCO divider used? What is the CLK input duty cycle? (The internal VCO has a 50% duty cycle.) Table 36.
AD9517-3 Data Sheet Phase Offset or Coarse Time Delay (0, 1) Channel Dividers—LVDS/CMOS Outputs Each channel divider allows for a phase offset, or a coarse time delay, to be programmed by setting register bits (see Table 38). These settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset, or delay, the rising edge of the output of the divider. This delay is with respect to a nondelayed output (that is, with a phase offset of zero).
Data Sheet AD9517-3 Duty Cycle and Duty-Cycle Correction (Divider 2 and Divider 3) The same duty cycle and DCC considerations apply to Divider 2 and Divider 3 as to Divider 0 and Divider 1 (see the Duty Cycle and Duty-Cycle Correction (0, 1) section); however, with these channel dividers, the number of possible configurations is even more complex. Duty-cycle correction on Divider 2 and Divider 3 requires the following channel divider conditions: • • • • An even DX.Y must be set as MX.Y = NX.
AD9517-3 Data Sheet Table 44. Divider 2 and Divider 3 Duty Cycle; VCO Divider Not Used; Duty Cycle Correction On (DCCOFF = 0) X% X% 50% X% 50% X% 50% X% 50% X% DX.1 DX.2 NX.1 + MX.1 + 2 1 Even (NX.1 = MX.1) 1 Even (NX.1 = MX.1) Odd (MX.1 = NX.1 + 1) Odd (MX.1 = NX.1 + 1) Even (NX.1 = MX.1) Even (NX.1 = MX.1) Odd (MX.1 = NX.1 + 1) Odd (MX.1 = NX.1 + 1) Odd (MX.1 = NX.1 + 1) Odd (MX.1 = NX.1 + 1) NX.2 + MX.2 + 2 1 1 Output Duty Cycle 50% 50% 1 1 X% (High) 50% Δt = Φx.1 × TX.1 + ΦX.2 × Tx.
Data Sheet AD9517-3 Synchronization of the outputs is executed in several ways, as follows: Calculating the Fine Delay The following values and equations are used to calculate the delay of the delay block. • IRAMP (µA) = 200 × (Ramp Current + 1) • Number of Capacitors = Number of Bits = 0 in Ramp Capacitors + 1 Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1. • Delay Range (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) × 1.3286 No.
AD9517-3 Data Sheet CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC INPUT TO VCO DIVIDER 1 1 INPUT TO CHANNEL DIVIDER 2 3 4 5 6 7 8 9 10 11 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 06427-073 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT Figure 57.
Data Sheet AD9517-3 LVPECL Outputs—OUT0 to OUT3 3.5mA The LVPECL differential voltage (VOD) is selectable from ~400 mV to ~960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]). The LVPECL outputs have dedicated pins for power supply (VS_LVPECL), allowing a separate power supply to be used. VS_LVPECL can be from 2.5 V to 3.3 V.
AD9517-3 Data Sheet POWER-DOWN MODES In asynchronous power-down mode, the device powers down as soon as the registers are updated. Chip Power-Down via PD The AD9517 can be put into a power-down condition by pulling the PD pin low. Power-down turns off most of the functions and currents inside the AD9517. The chip remains in this power-down state until PD is brought back to logic high.
Data Sheet AD9517-3 SERIAL CONTROL PORT The AD9517 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9517 serial control port is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR® protocols. The serial control port allows read/write access to all registers that configure the AD9517.
AD9517-3 Data Sheet Read If the instruction word is for a read operation, the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 3 as determined by [W1:W0]. If N = 4, the read operation is in streaming mode, continuing until CS is raised. Streaming mode does not skip over reserved or blank registers. The readback data is valid on the falling edge of SCLK. The default mode of the AD9517 serial control port is the bidirectional mode.
Data Sheet AD9517-3 Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16-BIT INSTRUCTION HEADER D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 06427-038 DON'T CARE Figure 64.
AD9517-3 Data Sheet tS tC CS tCLK tHIGH SCLK tLOW tDS SDIO BIT N BIT N + 1 Figure 69. Serial Control Port Timing—Write Table 50.
Data Sheet AD9517-3 THERMAL PERFORMANCE Table 51. Thermal Parameters for the 48-Lead LFCSP Symbol θJA θJMA θJMA θJB ΨJB ΨJB ΨJB θJC ΨJT ΨJT ΨJT Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Junction-to-ambient thermal resistance, natural convection per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
AD9517-3 Data Sheet CONTROL REGISTERS CONTROL REGISTER MAP OVERVIEW Table 52. Control Register Map Overview Reg. Addr.
Data Sheet AD9517-3 Reg. Addr.
AD9517-3 Data Sheet Reg. Addr.
Data Sheet AD9517-3 CONTROL REGISTER MAP DESCRIPTIONS Table 53 through Table 62 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2]. Table 53. Serial Port Configuration and Part ID Reg.
AD9517-3 Data Sheet Table 54. PLL Reg. Addr.
Data Sheet Reg. Addr. (Hex) 0x016 0x017 Bits [2:0] [7:2] Name Prescaler P STATUS pin control AD9517-3 Description Prescaler: DM = dual modulus and FD = fixed divide. 2 1 0 Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 (2/3 mode). 0 1 1 DM Divide-by-4 (4/5 mode). 1 0 0 DM Divide-by-8 (8/9 mode). 1 0 1 DM Divide-by-16 (16/17 mode). 1 1 0 DM Divide-by-32 (32/33 mode) (default). 1 1 1 FD Divide-by-3. Selects the signal that is connected to the STATUS pin.
AD9517-3 Data Sheet Reg. Addr. (Hex) 0x017 Bits [1:0] Name Antibacklash pulse width 0x018 [6:5] Lock detect counter 4 Digital lock detect window 3 Disable digital lock detect [2:1] VCO cal divider 0 VCO cal now [7:6] R, A, B counters SYNC pin reset [5:3] [2:0] R path delay N path delay 0x019 Description 1 0 Antibacklash Pulse Width (ns) 0 0 2.9 (default). This is the recommended setting; it does not normally need to be changed. 0 1 1.3.
Data Sheet Reg. Addr. (Hex) 0x01A Bits 6 Name Reference frequency monitor threshold [5:0] LD pin control AD9517-3 Description Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO frequency monitor’s detection threshold (see Table 16: REF1, REF2, and VCO frequency status monitor parameter). 0: frequency valid if frequency is above the higher frequency threshold (default). 1: frequency valid if frequency is above the lower frequency threshold.
AD9517-3 Reg. Addr. (Hex) 0x01B 0x01C Data Sheet Bits 7 Name VCO frequency monitor 6 REF2 (REFIN) frequency monitor 5 REF1 (REFIN) frequency monitor [4:0] REFMON pin control 7 6 Disable switchover deglitch Select REF2 5 Use REF_SEL pin [4:3] Reserved Description Enables or disables VCO frequency monitor. 0: disables VCO frequency monitor (default). 1: enables VCO frequency monitor. Enables or disables REF2 frequency monitor. 0: disables REF2 frequency monitor (default).
Data Sheet Reg. Addr. (Hex) 0x01D Bits 2 Name REF2 power-on 1 REF1 power-on 0 Differential reference 4 PLL status register disable 3 LD pin comparator enable 2 Holdover enable 1 External holdover control 0x01F 0 Holdover enable 6 VCO cal finished 5 Holdover active 4 REF2 selected 3 VCO frequency > threshold 2 REF2 frequency > threshold 1 REF1 frequency > threshold 0 Digital lock detect AD9517-3 Description This bit turns the REF2 power on. 0: REF2 power off (default).
AD9517-3 Data Sheet Table 55. Fine Delay Adjust—OUT4 to OUT7 Reg. Addr. (Hex) 0x0A0 Bits 0 Name OUT4 delay bypass 0x0A1 [5:3] OUT4 ramp capacitors [2:0] OUT4 ramp current 0x0A2 [5:0] OUT4 delay fraction 0x0A3 0 OUT5 delay bypass 0x0A4 [5:3] OUT5 ramp capacitors Description Bypasses or uses the delay function. 0: uses delay function. 1: bypasses delay function (default). Selects the number of ramp capacitors used by the delay function.
Data Sheet Reg. Addr. (Hex) 0x0A4 Bits [2:0] Name OUT5 ramp current 0x0A5 [5:0] OUT5 delay fraction 0x0A6 0 OUT6 delay bypass 0x0A7 [5:3] OUT6 ramp capacitors [2:0] OUT6 ramp current 0x0A8 [5:0] OUT6 delay fraction 0x0A9 0 OUT7 delay bypass AD9517-3 Description Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale.
AD9517-3 Reg. Addr. (Hex) 0x0AA 0x0AB Data Sheet Bits [5:3] Name OUT7 ramp capacitors [2:0] OUT7 ramp current [5:0] OUT7 delay fraction Description Selects the number of ramp capacitors used by the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. 5 4 3 Number of Capacitors 0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 Ramp current for the delay function.
Data Sheet Reg. Addr. (Hex) 0x0F1 0x0F4 0x0F5 Bits 4 Name OUT1 invert [3:2] OUT1 LVPECL differential voltage [1:0] OUT1 power-down 4 OUT2 invert [3:2] OUT2 LVPECL differential voltage [1:0] OUT2 power-down 4 OUT3 invert [3:2] OUT3 LVPECL differential voltage [1:0] OUT3 power-down AD9517-3 Description Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (VOD).
AD9517-3 Data Sheet Table 57. LVDS/CMOS Outputs Reg. Addr. (Hex) 0x140 0x141 Bits [7:5] Name OUT4 output polarity 4 OUT4 CMOS B 3 OUT4 select LVDS/CMOS [2:1] OUT4 LVDS output current 0 OUT4 power-down [7:5] OUT5 output polarity 4 OUT5 CMOS B 3 OUT5 select LVDS/CMOS [2:1] OUT5 LVDS output current Description In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity.
Data Sheet Reg. Addr. (Hex) 0x141 Bits 0 Name OUT5 power-down 0x142 [7:5] OUT6 output polarity 4 OUT6 CMOS B 3 OUT6 select LVDS/CMOS [2:1] OUT6 LVDS output current 0 OUT6 power-down [7:5] OUT7 output polarity 4 OUT7 CMOS B 3 OUT7 select LVDS/CMOS 0x143 AD9517-3 Description Powers down output (LVDS/CMOS). 0: power on. 1: power off (default). In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity.
AD9517-3 Reg. Addr. (Hex) 0x143 Data Sheet Bits [2:1] Name OUT7 LVDS output current 0 OUT7 power-down Description Sets output current level in LVDS mode. This has no effect in CMOS mode. 2 1 Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 Powers down output (LVDS/CMOS). 0: power on. 1: power off (default). Table 58. LVPECL Channel Dividers Reg. Addr.
Data Sheet Reg. Addr. (Hex) 0x197 Bits 4 Name Divider 1 start high 0x198 [3:0] 1 Divider 1 phase offset Divider 1 direct to output 0 Divider 1 DCCOFF AD9517-3 Description Selects clock output to start high or start low. 0: starts low (default). 1: starts high. Phase offset (default = 0x0). Connects OUT2 and OUT3 to Divider 2 or directly to VCO or CLK. 0: OUT2 and OUT3 are connected to Divider 1 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.
AD9517-3 Reg. Addr. (Hex) 0x19F 0x1A0 0x1A1 0x1A2 Data Sheet Bits [7:4] [3:0] [7:4] Name Phase Offset Divider 3.2 Phase Offset Divider 3.1 Low Cycles Divider 3.2 [3:0] High Cycles Divider 3.2 5 Bypass Divider 3.2 4 Bypass Divider 3.1 3 Divider 3 nosync 2 Divider 3 force high 1 Start High Divider 3.2 0 Start High Divider 3.1 0 Divider 3 DCCOFF Description Refer to LVDS/CMOS channel divider function description (default = 0x0).
Data Sheet AD9517-3 Table 60. VCO Divider and CLK Input Reg. Addr (Hex) 0x1E0 Bits [2:0] Name VCO divider 0x1E1 4 Power down clock input section 3 Power down VCO clock interface 2 Power down VCO and CLK 1 Select VCO or CLK 0 Bypass VCO divider 0x1E1 Description 2 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 Divide 2. 3. 4 (default). 5. 6. Output static. Note that setting the VCO divider static should occur only after VCO calibration. 1 1 0 Output static.
AD9517-3 Data Sheet APPLICATIONS INFORMATION Within the AD9517 family, lower VCO frequencies generally result in slightly lower jitter. The difference in integrated jitter (from 12 kHz to 20 MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.45 GHz to 2.95 GHz) of the AD9517 family.
Data Sheet AD9517-3 LVPECL CLOCK DISTRIBUTION The LVPECL outputs of the AD9517 provide the lowest jitter clock signals that are available from the AD9517. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 59 shows the LVPECL output stage. In most applications, an LVPECL far-end Thevenin termination (see Figure 71) or Y-termination (see Figure 72) is recommended.
AD9517-3 Data Sheet The AD9517 provides four clock outputs (OUT4 to OUT7) that are selectable as either CMOS or LVDS level outputs. When selected as CMOS, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as noninverting or inverting. These outputs are 3.3 V CMOS compatible. Whenever single-ended CMOS clocking is used, some of the following general guidelines should be used. Termination at the far end of the PCB trace is a second option.
Data Sheet AD9517-3 OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 PIN 1 INDICATOR 6.85 6.75 SQ 6.65 1 0.50 REF *5.55 EXPOSED PAD 5.50 SQ 5.45 12 25 0.50 0.40 0.30 TOP VIEW 1.00 0.85 0.80 12° MAX 13 24 BOTTOMVIEW 0.22 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 48 36 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
AD9517-3 Data Sheet NOTES ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06427-0-3/13(E) Rev.