Datasheet

AD9518-1 Data Sheet
Rev. C | Page 10 of 64
SERIAL CONTROL PORT
Table 13.
Parameter Min Typ Max Unit Test Conditions/Comments
CS
(INPUT)
CS
has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 3 µA
Input Logic 0 Current 110 µA
Input Capacitance 2 pF
SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current 110 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
SDIO (WHEN INPUT)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 10 nA
Input Logic 0 Current 20 nA
Input Capacitance
2
pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/t
SCLK
) 25 MHz
Pulse Width High, t
HIGH
16 ns
Pulse Width Low, t
LOW
16 ns
SDIO to SCLK Setup, t
DS
2 ns
SCLK to SDIO Hold, t
DH
1.1 ns
SCLK to Valid SDIO and SDO, t
DV
8 ns
CS
to SCLK Setup and Hold, t
S
, t
H
2
ns
CS
Minimum Pulse Width High, t
PWH
3 ns
PD
,
SYNC
, AND
RESET
PINS
Table 14.
Parameter Min Typ Max Unit Test Conditions/Comments
INPUT CHARACTERISTICS These pins each have a 30 kΩ internal pull-up
resistor
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 1 µA
Logic 0 Current
110
µA
Capacitance
2
pF
RESET
TIMING
Pulse Width Low 50 ns
SYNC
TIMING
Pulse Width Low 1.5 High speed
clock
cycles
High speed clock is CLK input signal