Datasheet

Data Sheet AD9518-1
Rev. C | Page 11 of 64
LD, STATUS, AND REFMON PINS
Table 15.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs;
see
Table 44, Register 0x017, Register 0x01A, and
Register 0x01B
Output Voltage High (V
OH
) 2.7 V
Output Voltage Low (V
OL
) 0.4 V
MAXIMUM TOGGLE RATE 100 MHz Applies when mux is set to any divider or counter output,
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; beware that spurs may
couple to output when any of these pins are toggling
ANALOG LOCK DETECT
Capacitance
3
pF
On-chip capacitance; used to calculate RC time constant
for analog lock detect readback; use a pull-up resistor
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range 1.02 MHz Frequency above which the monitor always indicates the
presence of the reference
Extended Range (REF1 and REF2 Only) 8 kHz Frequency above which the monitor always indicates the
presence of the reference
LD PIN COMPARATOR
Trip Point 1.6 V
Hysteresis 260 mV
POWER DISSIPATION
Table 16.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER DISSIPATION, CHIP
Power-On Default 0.76 1.0 W No clock; no programming; default register values;
does not include power dissipated in external resistors
Full Operation 1.1 1.7 W PLL on; internal VCO = 2476 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 619 MHz;
does not include power dissipated in external resistors
PD
Power-Down 75 185 mW
PD
pin pulled low; does not include power dissipated
in terminations
PD
Power-Down, Maximum Sleep 31 mW
PD
pin pulled low; PLL power-down, Register 0x010[1:0] =
01b; SYNC power-down, Register 0x230[2] = 1b; REF for
distribution power-down, Register 0x230[1] = 1b
V
CP
Supply 4 4.8 mW PLL operating; typical closed-loop configuration
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power delta when a function is enabled/disabled
VCO Divider 30 mW VCO divider bypassed
REFIN (Differential) 20 mW All references off to differential reference enabled
REF1, REF2 (Single-Ended) 4 mW All references off to REF1 or REF2 enabled; differential
reference not enabled
VCO 70 mW CLK input selected to VCO selected
PLL 75 mW PLL off to PLL on, normal operation; no reference
enabled
Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32
LVPECL Channel (Divider Plus Output Driver) 160 mW No LVPECL output on to one LVPECL output on,
independent of frequency
LVPECL Driver 90 mW Second LVPECL output turned on, same channel