Datasheet

AD9518-1 Data Sheet
Rev. C | Page 56 of 64
Table 46. LVPECL Channel Dividers
Reg.
Addr.
(Hex) Bits Name Description
0x190 [7:4] Divider 0 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0] Divider 0 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x191 7 Divider 0 bypass Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
6 Divider 0 nosync No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5 Divider 0 force high Forces divider output to high. This requires that the Divider 0 nosync bit (Bit 6) also be set.
This bit has no effect if the Divider 0 bypass bit (Bit 7) is set.
0: divider output forced to low (default).
1: divider output forced to high.
4
Divider 0 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0] Divider 0 phase offset Phase offset (default = 0x0).
0x192 1 Divider 0 direct to output Connects OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
0 Divider 0 DCCOFF Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x193 [7:4] Divider 1 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0xB).
[3:0] Divider 1 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0xB).
0x194 7 Divider 1 bypass Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6 Divider 1 nosync No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 1 force high
Forces divider output to high. This requires that the Divider 1 nosync bit (Bit 6) also be set.
This bit has no effect if the Divider 1 bypass bit (Bit 7) is set.
0: divider output forced to low (default).
1: divider output forced to high.
4 Divider 1 start high Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0] Divider 1 phase offset Phase offset (default = 0x0).