Datasheet

AD9518-1 Data Sheet
Rev. C | Page 60 of 64
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs (because they are open emitter) require a
dc termination to bias the output transistors. The simplified
equivalent circuit in Figure 43 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 53) or Y-termination (see Figure 54) is recommended.
In each case, the V
S
of the receiving buffer should match the
V
S_LVPECL
voltage. If it does not, ac coupling is recommended (see
Figure 55). In the case of Figure 55, pull-down resistors of <150 Ω
are not recommended when V
S_LV PECL
= 3.3 V; if used, damage to
the LVPECL drivers may result. The minimum recommended
pull-down resistor size for V
S_ LVPEC L
= 2.5 V is 100 Ω.
The resistor network is designed to match the transmission line
impedance (50 Ω) and the switching threshold (V
S
− 1.3 V).
V
S_LVPECL
LVPECL
50Ω
50Ω
SINGLE-ENDED
(NOT COUPLED)
V
S
V
S_DRV
LVPECL
127Ω
127Ω
83Ω
83Ω
06430-145
Figure 53. LVPECL Far-End Thevenin Termination
V
S_LVPECL
LVPECL
Z
0
= 50Ω
V
S
= 3.3V
LVPECL
50Ω
50Ω
50Ω
Z
0
= 50Ω
06430-147
Figure 54. DC-Coupled 3.3 V LVPECL Y-Termination
V
S_LVPECL
LVPECL
100Ω DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
V
S
LVPECL
100Ω
0.1nF
0.1nF
200Ω
200Ω
06430-146
Figure 55. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 54, where V
S_ LVPECL
= 2.5 V, the 50 Ω termination
resistor that is connected to ground should be changed to 19 Ω.
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below V
OL
of the LVPECL
driver. In this case, V
S_LVPE CL
on the AD9518 should equal V
S
of
the receiving buffer. Although the resistor combination shown
in Figure 54 results in a dc bias point of V
S_LVPEC L
− 2 V, the actual
common-mode voltage is V
S_LVPE CL
− 1.3 V because there is
additional current flowing from the AD9518 LVPECL driver
through the pull-down resistor.
The circuit is identical when V
S_LVPECL
= 2.5 V, except that the pull-
down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.