Datasheet

Data Sheet AD9518-1
Rev. C | Page 9 of 64
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL and
VCO; uses rising edge of clock signal
CLK = 622.08 MHz; LVPECL = 622.08 MHz;
Divider = 1
40 fs rms BW = 12 kHz to 20 MHz
CLK = 622.08 MHz; LVPECL = 155.52 MHz;
Divider = 4
80 fs rms BW = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16 215 fs rms Calculated from SNR of ADC method; DCC not used
for even divides
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 245 fs rms Calculated from SNR of ADC method; DCC on
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
210 fs rms Calculated from SNR of ADC method