Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9520-0BCPZ

12 LVPECL/24 CMOS Output Clock

Generator with Integrated 2.8 GHz VCO

Data Sheet

AD9520-0

Rev. A Document Feedback

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FEATURES

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 2.53 GHz to 2.95 GHz

Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz

1 differential or 2 single-ended reference inputs

Accepts CMOS, LVDS, or LVPECL references to 250 MHz

Accepts 16.62 MHz to 33.3 MHz crystal for reference input

Optional reference clock doubler

Reference monitoring capability

Automatic/manual reference holdover and reference

switchover modes, with revertive switching

Glitch-free switchover between references

Automatic recovery from holdover

Digital or analog lock detect, selectable

Optional zero delay operation

Twelve 1.6 GHz LVPECL outputs divided into 4 groups

Each group of 3 outputs shares a 1-to-32 divider with

phase delay

Additive output jitter as low as 225 fs rms

Channel-to-channel skew grouped outputs < 16 ps

Each LVPECL output can be configured as 2 CMOS outputs

(for f

OUT

≤ 250 MHz)

Automatic synchronization of all outputs on power-up

Manual output synchronization available

SPI- and I²C-compatible serial control port

64-lead LFCSP

Nonvolatile EEPROM stores configuration settings

APPLICATIONS

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10GFC,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

ATE and high performance instrumentation

Broadband infrastructures

GENERAL DESCRIPTION

The AD9520-0

provides a multi-output clock distribution

function with subpicosecond jitter performance, along with an

on-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHz

to 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz

can also be used.

FUNCTIONAL BLOCK DIAGRAM

OPTIONAL

REF1

REF2

CLK

SWITCHOVER

AND MONITOR

PLL

DIVIDER

AND MUXES

ZERO

DELAY

VCO

STATUS

MONITOR

SPI/I

C CONTROL

PORT AND

DIGITAL LOGIC

EEPROM

AD9520

OUT0

OUT1

OUT2

DIV/Φ

OUT3

OUT4

OUT5

DIV/Φ

OUT6

OUT7

OUT8

DIV/Φ

OUT9

OUT10

OUT11

DIV/Φ

LVPECL/

CMOS

REFIN

07213-001

Figure 1.

The AD9520 serial interface supports both SPI and I²C ports.

An in-package EEPROM, which can be programmed through the

serial interface, can store user-defined register settings for

power-up and chip reset.

The AD9520 features 12 LVPECL outputs in four groups. Any

of the 1.6 GHz LVPECL outputs can be reconfigured as two

250 MHz CMOS outputs. If an application requires LVDS

drivers instead of LVPECL drivers, refer to the AD9522.

Each group of three outputs has a divider that allows both the

divide ratio (from 1 to 32) and the phase offset or coarse time

delay to be set.

The AD9520 is available in a 64-lead LFCSP and can be operated

from a single 3.3 V supply. The external VCO can have an

operating voltage of up to 5.5 V. A separate output driver power

supply can be from 2.375 V to 3.465 V.

The AD9520-0 is specified for operation over the standard

industrial range of −40°C to +85°C.

AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-0 is used, it refers to that specific member of the

AD9520 family.

Summary of content (80 pages)

PAGE 1
Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO AD9520-0 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.
PAGE 2
AD9520-0 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions........................... 18 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 21 General Description .........................................................................
PAGE 3
Data Sheet AD9520-0 REVISION HISTORY 8/13—Rev. 0 to Rev. A Changes to Features Section, Applications Section, and General Description Section ............................................................ 1 Changes to Table 2 ............................................................................ 4 Changes to Input Frequency Parameter; Change to Input Sensitivity, Differential Parameter Test Conditions/Comments, Table 3 ...................................................................................
PAGE 4
AD9520-0 Data Sheet SPECIFICATIONS Typical is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter POWER PINS VS VS_DRV VCP CURRENT SET RESISTORS RSET Pin Resistor CPRSET Pin Resistor Min Typ Max Unit Test Conditions/Comments 3.135 2.375 VS 3.3 3.465 VS 5.25 V V V 3.3 V ± 5% Nominally 2.5 V to 3.
PAGE 5
Data Sheet Parameter Pulse Width High/Low AD9520-0 Max Unit ns 33.33 30 MHz Ω 100 45 50 1.3 2.9 6.0 MHz MHz MHz ns ns ns ICP Sink/Source High Value 4.8 mA Low Value 0.60 mA Crystal Oscillator Crystal Resonator Frequency Range Maximum Crystal Motional Resistance PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency Reference Input Clock Doubler Frequency Antibacklash Pulse Width Min 1.8 Typ 16.62 0.
PAGE 6
AD9520-0 Parameter PHASE OFFSET IN ZERO DELAY Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector 2 500 kHz PFD Frequency 1 MHz PFD Frequency 10 MHz PFD Frequency 50 MHz PFD Frequency PLL Figure of
PAGE 7
Data Sheet AD9520-0 CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min Max Unit 01 01 2.4 2.0 GHz GHz 01 1.6 GHz Input Sensitivity, Differential Typ 150 Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance 1 1.3 1.3 3.9 1.57 150 4.7 2 mV p-p 2 V p-p 1.8 1.8 V V mV p-p kΩ pF 5.
PAGE 8
AD9520-0 Parameter Source Current Static Dynamic Sink Current Static Dynamic Data Sheet Min Typ Max Unit Test Conditions/Comments Damage to the part can result if values are exceeded 20 16 mA mA 8 16 mA mA Typ Max Unit 130 170 ps 130 170 ps 1050 970 1.0 1280 1180 ps ps ps/°C 5 16 ps Termination = 50 Ω to VS_DRV − 2 V VS_DRV = 3.3 V 5 5 20 45 ps ps VS_DRV = 2.5 V VS_DRV = 3.3 V 5 60 190 ps ps VS_DRV = 2.5 V VS_DRV = 3.3 V and 2.
PAGE 9
Data Sheet AD9520-0 Timing Diagrams DIFFERENTIAL SINGLE-ENDED 80% 80% LVPECL CMOS 10pF LOAD 20% tRC Figure 2. LVPECL Timing, Differential Figure 4. CMOS Timing, Single-Ended, 10 pF Load tCLK CLK 07213-060 tPECL tCMOS tFC Figure 3. CLK/CLK to Clock Output Timing, DIV = 1 Rev.
PAGE 10
AD9520-0 Data Sheet CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6.
PAGE 11
Data Sheet AD9520-0 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter LVPECL ABSOLUTE PHASE NOISE Min VCO = 2.95 GHz; Output = 2.95 GHz 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset VCO = 2.75 GHz; Output = 2.75 GHz 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset VCO = 2.55 GHz; Output = 2.
PAGE 12
AD9520-0 Data Sheet CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min LVPECL = 245.76 MHz; PLL LBW = 125 Hz Typ Max 54 77 109 79 114 163 124 176 259 LVPECL = 122.88 MHz; PLL LBW = 125 Hz LVPECL = 61.44 MHz; PLL LBW = 125 Hz Unit fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms Test Conditions/Comments Application example based on a typical setup using an external 245.
PAGE 13
Data Sheet AD9520-0 SERIAL CONTROL PORT—SPI MODE Table 13. Parameter CS (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Min Max Unit 0.8 3 −110 V V µA µA 2 pF 2.
PAGE 14
AD9520-0 Data Sheet SERIAL CONTROL PORT—I²C MODE Table 14. Parameter SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage Input Logic 0 Voltage Input Current with an Input Voltage Between 0.1 × VS and 0.9 × VS Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSPIKE SDA (WHEN OUTPUTTING DATA) Output Logic 0 Voltage at 3 mA Sink Current Output Fall Time from VIHMIN to VILMAX with a Bus Capacitance from 10 pF to 400 pF TIMING Min Typ Unit 0.
PAGE 15
Data Sheet AD9520-0 PD, EEPROM, RESET, AND SYNC PINS Table 15. Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming SYNC TIMING Pulse Width Low Min Typ Max Unit 0.8 1 −110 V V µA µA 2 pF 2.
PAGE 16
AD9520-0 Data Sheet POWER DISSIPATION Table 18. Parameter POWER DISSIPATION, CHIP Typ Max Unit Power-On Default PLL Locked; One LVPECL Output Enabled 1.32 0.55 1.5 0.64 W W PLL Locked; One CMOS Output Enabled 0.52 0.62 W Distribution Only Mode; VCO Divider On; One LVPECL Output Enabled Distribution Only Mode; VCO Divider Off; One LVPECL Output Enabled Maximum Power, Full Operation 0.39 0.46 W 0.36 0.42 W 1.5 1.
PAGE 17
Data Sheet AD9520-0 ABSOLUTE MAXIMUM RATINGS Table 19.
PAGE 18
AD9520-0 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 REFIN (REF1) REFIN (REF2) CPRSET VS VS GND RSET VS OUT0 (OUT0A) OUT0 (OUT0B) VS_DRV OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) VS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9520 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OUT3 (OUT3A) OUT3 (OUT3B) VS_DRV OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) VS VS OUT8 (OUT8B) OUT8 (OUT8A) O
PAGE 19
Data Sheet AD9520-0 Pin No. 15 Input/ Output I Pin Type 3.3 V CMOS Mnemonic CS 16 I 3.3 V CMOS SCLK/SCL 17 18 19, 59 20 I/O O I I SDIO/SDA SDO GND SP1 21 I 22 I 3.3 V CMOS 3.3 V CMOS GND Three-level logic Three-level logic 3.3 V CMOS 23 24 25 I I O RESET PD OUT9 (OUT9A) 26 O 27, 35, 46, 54 28 I 3.3 V CMOS 3.
PAGE 20
AD9520-0 Pin No.
PAGE 21
Data Sheet AD9520-0 TYPICAL PERFORMANCE CHARACTERISTICS 350 5 3 CHANNELS—6 LVPECL CURRENT FROM CP PIN (mA) CURRENT (mA) 300 3 CHANNELS—3 LVPECL 250 2 CHANNELS—2 LVPECL 200 150 4 PUMP DOWN PUMP UP 3 2 1 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) 0 07213-108 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V) Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off), LVPECL Outputs Terminated 50 Ω to VS_DRV − 2 V 07213-111 1 CHANNEL—1 LVPECL Figure 9.
PAGE 22
AD9520-0 Data Sheet –208 3.5 VS_DRV = 3.3V 3.0 VS_DRV = 3.135V –212 VS_DRV = 2.5V 2.5 –214 VOH (V) PLL FIGURE OF MERIT (dBc/Hz) –210 –216 VS_DRV = 2.35V 2.0 1.5 –218 DIFFERENTIAL INPUT 1.0 –220 0.5 –222 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 INPUT SLEW RATE (V/ns) 0 10k 07213-114 –224 1k 100 RESISTIVE LOAD (Ω) 07213-118 SINGLE-ENDED INPUT Figure 15. CMOS Output VOH (Static) vs. RLOAD (to Ground) Figure 12. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN 0 1.2 –10 0.
PAGE 23
Data Sheet AD9520-0 4.0 3.2 3.5 2.8 3.0 1.6 1.2 2.5 2.0 0.8 1.0 0.4 0.5 0 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) 10pF 1.5 20pF 0 0 100 200 300 400 500 600 700 FREQUENCY (MHz) 07213-124 AMPLITUDE (V) 2pF 2.0 07213-018 AMPLITUDE (V) 2.4 Figure 21. CMOS Output Swing vs. Frequency and Capacitive Load Figure 18. CMOS Output with 10 pF Load at 25 MHz –40 2pF LOAD 3.2 –50 2.8 –60 AMPLITUDE (V) 2.4 PHASE NOISE (dBc/Hz) 10pF LOAD 2.0 1.6 1.2 0.
PAGE 24
AD9520-0 Data Sheet –40 –100 –50 –110 –70 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –60 –80 –90 –100 –110 –120 –130 –120 –130 –140 –150 10k 100k 1M 10M 100M FREQUENCY (Hz) –160 10 07213-025 –150 1k –110 –120 PHASE NOISE (dBc/Hz) 10k 100k 1M 10M 100M 100M –130 –140 –150 –170 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 25. Additive (Residual) Phase Noise, CLK-to-LVPECL at 245.76 MHz, Divide-by-1 Figure 28.
PAGE 25
Data Sheet AD9520-0 –100 –80 INTEGRATED RMS JITTER (12kHz TO 20MHz): 652 fs –90 –100 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –110 –120 –130 –140 –110 –120 –130 –140 –150 10k 100k 1M 10M 100M FREQUENCY (Hz) –160 1k 07213-033 –160 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 07213-034 –150 NOTES 1. THE LOOP FILTER USED TO GENERATE THIS PLOT IS SHOWN IN FIGURE 41. NOTES 1. THE LOOP FILTER USED TO GENERATE THIS PLOT IS SHOWN IN FIGURE 42. Figure 30.
PAGE 26
AD9520-0 Data Sheet TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.
PAGE 27
Data Sheet AD9520-0 DETAILED BLOCK DIAGRAM VS GND RSET DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP REFMON PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 C
PAGE 28
AD9520-0 Data Sheet THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9520 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 50 to Table 61). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers.
PAGE 29
Data Sheet AD9520-0 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 CLK OUT0 1 DIVIDE BY 1
PAGE 30
AD9520-0 Data Sheet Mode 1—Clock Distribution or External VCO < 1600 MHz When the external clock source to be distributed or the external VCO/VCXO is <1600 MHz, a configuration that bypasses the VCO divider can be used. This is the only difference from Mode 2. Bypassing the VCO divider limits the frequency of the clock source to <1600 MHz (due to the maximum input frequency allowed at the channel dividers).
PAGE 31
Data Sheet AD9520-0 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 CLK OUT0 1 DIVIDE BY 1
PAGE 32
AD9520-0 Data Sheet Mode 2—High Frequency Clock Distribution; CLK or External VCO > 1600 MHz When the internal PLL is used with an external VCO, the PLL must be turned on. The AD9520 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/divide-by-5/ divide-by-6).
PAGE 33
Data Sheet AD9520-0 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 CLK OUT0 1 DIVIDE BY 1
PAGE 34
AD9520-0 Data Sheet Phase-Locked Loop (PLL) VS RSET GND REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF REFIN BYPASS LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK VS_DRV FROM CHANN
PAGE 35
Data Sheet AD9520-0 C1 62pF VCO 31pF R2 R1 BYPASS C1 C2 C3 07213-142 CHARGE PUMP CBP = 220nF Figure 39. Example of External Loop Filter for a PLL Using the Internal VCO When using an external VCO, ensure that the external loop filter is referenced to ground. See Figure 40 for an example of an external loop filter for a PLL using an external VCO. AD9520 Figure 41. Typical PLL Loop Filter Used for Clock Generation CLK/CLK R2 R1 C1 C2 C3 07213-143 CHARGE PUMP R2 3kΩ CP C1 1.5nF C2 4.
PAGE 36
AD9520-0 Data Sheet The differential reference input receiver is powered down when the differential reference input is not selected or when the PLL is powered down. The single-ended buffers power down when the PLL is powered down or when their respective individual power-down registers are set. When the differential mode is selected, the single-ended inputs are powered down. clock disappears.
PAGE 37
Data Sheet AD9520-0 Prescaler The prescaler of the AD9520 allows for two modes of operation: a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM) mode where the prescaler divides by P and (P + 1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of operation are given in Table 54, Register 0x016[2:0]. Not all modes are available at all frequencies (see Table 2).
PAGE 38
AD9520-0 Data Sheet By selecting the proper output through the mux on each pin, the DLD function is available at the LD, STATUS, and REFMON pins. The digital lock detect circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value (the lock threshold). The loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold).
PAGE 39
Data Sheet AD9520-0 External VCXO/VCO Clock Input (CLK/CLK) This differential input is used to drive the AD9520 clock distribution section. This input can receive up to 2.4 GHz. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors. CLOCK INPUT STAGE When using this mode, set the channel dividers to ignore the SYNC pin (at least after an initial SYNC event).
PAGE 40
AD9520-0 Data Sheet The following registers affect the automatic/internal holdover function: A flowchart of the automatic/internal holdover function operation is shown in Figure 47. • PLL ENABLED LOOP OUT OF LOCK. DIGITAL LOCK DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK, AS DETERMINED BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD. NO DLD == LOW YES • NO • REG 0x01D[3]: LD PIN COMPARATOR ENABLE. 0b = DISABLE; 1b = ENABLE. WHEN DISABLED, THE HOLDOVER FUNCTION ALWAYS SENSES THE LD PIN AS HIGH.
PAGE 41
Data Sheet AD9520-0 VS GND RSET DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF REFIN BYPASS LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP REFMON PROGRAMMABLE R DELAY REF_SEL HOLD VCO STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK FROM CHANNEL DIVIDER 0 1 VS_DRV 07213-
PAGE 42
AD9520-0 Data Sheet The VCO calibration clock divider is set as shown in Table 54 (Register 0x018[2:1]). The calibration divider divides the PFD frequency (reference frequency divided by R) down to the calibration clock. The calibration occurs at the PFD frequency divided by the calibration divider setting. Lower VCO calibration clock frequencies result in longer times for a calibration to be done.
PAGE 43
Data Sheet AD9520-0 REFIN/ REFIN R DIVIDER AD9520 R DELAY PFD N DIVIDER LOOP FILTER CP N DELAY REG 0x01E[1] = 1 MUX1 MUX3 INTERNAL FEEDBACK PATH ZERO DELAY FEEDBACK CLOCK LF EXTERNAL FEEDBACK PATH REG 0x01E[2] DIVIDE BY 1, 2, 3, 4, 5, OR 6 ZERO DELAY CLK/CLK CHANNEL DIVIDER 0 OUT0 TO OUT2 CHANNEL DIVIDER 1 OUT3 TO OUT5 CHANNEL DIVIDER 2 OUT6 TO OUT8 CHANNEL DIVIDER 3 OUT9 TO OUT11 0 07213-053 1 Figure 49.
PAGE 44
AD9520-0 Data Sheet outputs. However, the LVPECL outputs may not be able to meet the VOD specification in Table 4 at the highest frequencies. In addition, the channel dividers allow a coarse phase offset or delay to be set. Depending on the division selected, the output can be delayed by up to 15 input clock cycles. For example, if the frequency at the input of the channel divider is 1 GHz, the channel divider output can be delayed by up to 15 ns.
PAGE 45
Data Sheet AD9520-0 The channel dividers feeding the output drivers contain one 2-to-32 frequency divider. This divider provides for division-by-1 to division-by-32. Division-by-1 is accomplished by bypassing the divider. The dividers also provide for a programmable duty cycle, with optional duty-cycle correction when the divide ratio is odd. A phase offset or delay in increments of the input clock cycle is selectable.
PAGE 46
AD9520-0 Data Sheet Table 36 to Table 39 show the output duty cycle for various configurations of the channel divider and VCO divider. Table 36. Channel Divider Output Duty Cycle with VCO Divider ≠ 1; Input Duty Cycle Is 50% VCO Divider Even Odd = 3 Odd = 5 Even, odd Even, odd DX N+M+2 Channel divider bypassed Channel divider bypassed Channel divider bypassed Even Odd Disable Divider x DCC = 1b 50% 33.
PAGE 47
Data Sheet AD9520-0 Note that the value stored in the register equals the number of cycles minus one. For example, Register 0x190[7:4] = 0001b equals two low cycles (M = 2) for Divider 0. Let Δt = delay (in seconds). Δc = delay (in cycles of clock signal at input to DX). TX = period of the clock signal at the input of the divider, DX (in seconds). Φ= 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]. The channel divide-by is set as N = high cycles and M = low cycles.
PAGE 48
AD9520-0 Data Sheet CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC INPUT TO VCO DIVIDER 1 1 INPUT TO CHANNEL DIVIDER 2 3 4 5 6 7 9 8 11 10 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 07213-073 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT Figure 52.
PAGE 49
Data Sheet AD9520-0 LVPECL Output Drivers CMOS Output Drivers The LVPECL differential voltage (VOD) is selectable (from ~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to Register 0x0FB). The LVPECL outputs have dedicated pins for power supply (VS_DRV), allowing a separate power supply to be used. VS_DRV can be set to either 2.5 V or 3.3 V. The user can also individually configure each LVPECL output as a pair of CMOS outputs, which provides up to 24 CMOS outputs.
PAGE 50
AD9520-0 Data Sheet Hardware Reset via the RESET Pin RESET, a hard reset (an asynchronous hard reset is executed by briefly pulling RESET low), restores the chip either to the setting stored in the EEPROM (the EEPROM pin = 1b) or to the on-chip setting (the EEPROM pin = 0b). A hard reset also executes a SYNC operation, bringing the outputs into phase alignment according to the default settings.
PAGE 51
Data Sheet AD9520-0 SERIAL CONTROL PORT The AD9520 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9520 serial control port is compatible with most synchronous transfer formats, including Philips I²C, Motorola® SPI®, and Intel® SSR protocols.
PAGE 52
AD9520-0 MSB 2 3 TO 7 8 9 1 2 3 TO 7 9 8 S 10 P 07213-162 1 SCL ACKNOWLEDGE FROM SLAVE-RECEIVER 10 P 07213-163 ACKNOWLEDGE FROM SLAVE-RECEIVER 10 P 07213-164 SDA Data Sheet Figure 58. Acknowledge Bit SDA MSB = 0 ACKNOWLEDGE FROM SLAVE-RECEIVER 1 SCL 2 3 TO 7 8 9 1 ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 9 8 S Figure 59.
PAGE 53
Data Sheet AD9520-0 Data Transfer Format Send byte format—the send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A RAM Address High Byte A RAM Address Low Byte A P Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
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AD9520-0 Data Sheet SPI SERIAL PORT OPERATION Pin Descriptions SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and the read data bits transition on the falling edge of SCLK. This pin is internally pulled down by a 30 kΩ resistor to ground.
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Data Sheet AD9520-0 The default mode of the AD9520 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin. It is also possible to set the AD9520 to unidirectional mode (Register 0x000[7] = 1b and Register 0x000[0] = 1b). In unidirectional mode, the readback data appears on the SDO pin. (Bits[3:0]). This makes it irrelevant whether LSB first or MSB first is in effect.
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AD9520-0 Data Sheet CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 07213-038 DON'T CARE Figure 64.
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Data Sheet AD9520-0 tS tC CS tCLK tHIGH SCLK tLOW tDS SDIO BIT N BIT N + 1 07213-043 tDH Figure 69. Serial Control Port Timing—Write Table 47.
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AD9520-0 Data Sheet EEPROM OPERATIONS The AD9520 contains an internal EEPROM (nonvolatile memory). The EEPROM can be programmed by users to create and store a user-defined register setting file when the power is off. This setting file can be used for power-up and chip reset as a default setting. The EEPROM size is 512 bytes. Note that, to guarantee proper loading of the EEPROM during startup, a high-low-high pulse on the RESET pin should occur after the power supply has stabilized.
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Data Sheet AD9520-0 PROGRAMMING THE EEPROM BUFFER SEGMENT IO_UPDATE (Operational Code 0x80) The EEPROM buffer segment is a register space on the AD9520. The user can specify which groups of registers are stored to the EEPROM during EEPROM programming. Note that programming this register space is optional. The default power-up values for the EEPROM buffer segment allow storage of all the AD9520 register values from Register 0x000 to Register 0x231 to the EEPROM.
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AD9520-0 Data Sheet THERMAL PERFORMANCE Table 49. Thermal Parameters for 64-Lead LFCSP Symbol θJA θJMA θJMA ΨJB θJC ΨJT Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
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Data Sheet AD9520-0 REGISTER MAP Register addresses that are not listed in Table 50 are not used, and writing to those registers has no effect. Writing to register addresses that are marked as unused also has no effect. Table 50. Register Map Overview Addr.
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AD9520-0 Data Sheet Addr.
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Data Sheet Addr.
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AD9520-0 Data Sheet REGISTER MAP DESCRIPTIONS Table 51 to Table 61 provide a detailed description of each of the control register functions. Table 51. SPI Mode Serial Port Configuration Reg. Addr. (Hex) 0x000 Bits 7 Name SDO active 6 LSB first/addr incr 5 Soft reset 4 [3:0] Unused Mirror[7:4] 0x003 [7:0] Part ID (read only) 0x004 [7:1] 0 Unused Read back active registers Description Selects unidirectional or bidirectional data transfer mode.
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Data Sheet AD9520-0 Table 54. PLL Reg. Addr. (Hex) Bits Name 0x010 7 PFD polarity [6:4] CP current [3:2] CP mode [1:0] PLL power-down 0x011 [7:0] 14-bit R counter, Bits[7:0] (LSB) 0x012 [7:6] Unused [5:0] 14-bit R counter, Bits[13:8] (MSB) 0x013 [7:6] Unused [5:0] 6-bit A counter 0x014 [7:0] 13-bit B counter, Bits[7:0] (LSB) 0x015 [7:5] Unused [4:0] 13-bit B counter, Bits[12:8] (MSB) Set CP pin 0x016 7 to VCP/2 6 5 4 3 Description Sets the PFD polarity.
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AD9520-0 Reg. Addr. (Hex) Bits Name [2:0] Prescaler P 0x017 [7:2] STATUS pin control Data Sheet Description Prescaler: DM = dual modulus; FD = fixed divide. Prescaler P is part of the feedback divider. See the VCO/VCXO Feedback Divider N—P, A, and B section of the datasheet for details. Bit Bit Bit 2 1 0 Mode Prescaler Divide-by-1. 0 0 0 FD Divide-by-2. 0 0 1 FD Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0. 0 1 0 DM Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.
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Data Sheet Reg. Addr. (Hex) Bits Name [1:0] Antibacklash pulse width 0x018 7 Enable CMOS reference input dc offset [6:5] Lock detect counter AD9520-0 Description Bit Bit 1 0 Antibacklash Pulse Width (ns) 0 0 2.9 (default) 0 1 1.3 1 0 6.0 1 1 2.9 Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost. 0: disables dc offset (default). 1: enables dc offset.
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AD9520-0 Data Sheet Reg. Addr. (Hex) Bits Name [5:0] LD pin control 0x01B 7 6 5 Description Selects the signal that is connected to the LD pin. Level or Bit Bit Bit Bit Bit Bit Dynamic 1 5 4 3 2 0 Signal Signal at LD Pin 0 0 0 0 0 0 LVL Digital lock detect (high = lock; low = unlock, default). 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 1 HIZ Tristate (high-Z) LD pin.
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Data Sheet AD9520-0 Reg. Addr. (Hex) Bits Name [4:0] REFMON pin control 0x01C 7 6 5 4 3 2 1 0 Description Selects the signal that is connected to the REFMON pin. Level or Bit Bit Bit Bit Bit Dynamic 4 3 2 1 0 Signal Signal at REFMON Pin 0 0 0 0 0 LVL Ground, dc (default). 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode).
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AD9520-0 Reg. Addr. (Hex) Bits Name Enable 0x01D 7 STATUS_EEPROM at STATUS pin 6 Enable XTAL OSC 5 Enable clock doubler 4 Disable PLL status register 3 Enable LD pin comparator 2 1 Unused Enable external holdover Data Sheet Description Enables the STATUS_EEPROM signal at the STATUS pin. 0: the STATUS pin is controlled by the Register 0x017[7:2] selection. 1: selects the STATUS_EEPROM signal at the STATUS pin. This bit overrides the Register 0x017[7:2] selection (default).
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Data Sheet AD9520-0 Table 55. Output Driver Control Reg. Addr.
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AD9520-0 Data Sheet Table 56. LVPECL Channel Dividers Reg. Addr.
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Data Sheet Reg. Addr.
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AD9520-0 Reg. Addr. (Hex) Bits 0x19A 7 Name Divider 3 bypass 6 Divider 3 ignore SYNC 5 Divider 3 force high 4 Divider 3 start high [3:0] 0x19B [7:3] 2 Divider 3 phase offset Unused Channel 3 power-down 1 Channel 3 direct to output 0 Disable Divider 3 DCC Data Sheet Description Bypasses and powers down the divider; routes input to divider output. 0: uses divider (default). 1: bypasses divider. Ignores SYNC. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal.
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Data Sheet AD9520-0 Table 58. System Reg. Addr. (Hex) Bits 0x230 [7:4] 3 Name Unused Disable power on SYNC 2 Power down SYNC 1 Power down distribution reference 0 Soft SYNC Description Unused. Powers on SYNC mode. Used to disable the antiruntpulse circuitry. 0: enables the antiruntpulse circuitry (default). 1: disables the antiruntpulse circuitry. Powers down the SYNC function. 0: normal operation of the SYNC function (default). 1: powers down SYNC circuitry.
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AD9520-0 Data Sheet Table 61. EEPROM Control Reg. Addr. (Hex) Bits Name 0xB00 [7:1] Unused 0 STATUS_EEPROM (read only) 0xB01 [7:1] Unused 0 EEPROM data error (read only) 0xB02 [7:2] Unused 1 SOFT_EEPROM 0 Enable EEPROM write 0xB03 [7:1] Unused 0 REG2EEPROM Description Unused. This read-only register indicates the status of the data transfer between the EEPROM and the buffer register bank during the writing and reading of the EEPROM.
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Data Sheet AD9520-0 APPLICATIONS INFORMATION Within the AD9520 family, lower VCO frequencies generally result in slightly better jitter. The difference in integrated jitter (from 12 kHz to 20 MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.4 GHz to 2.95 GHz) of the AD9520 family.
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AD9520-0 Data Sheet LVPECL CLOCK DISTRIBUTION Far-End Thevenin Termination The LVPECL outputs of the AD9520 provide the lowest jitter clock signals available from the AD9520. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 54 shows the LVPECL output stage. Far-end Thevenin termination uses a resistor network to provide 50 Ω termination to a dc voltage that is below VOL of the LVPECL driver.
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Data Sheet AD9520-0 Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9520 do not supply enough current to provide a full voltage swing with a low impedance resistive, farend termination, as shown in Figure 75. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications.
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AD9520-0 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.25 0.18 0.60 MAX 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 16 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-12-2012-C 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.