Datasheet

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12 LVPECL/24 CMOS Output

Clock Generator

Data Sheet

AD9520-5

Rev. A Document Feedback

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FEATURES

Low phase noise, phase-locked loop (PLL)

Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz

1 differential or 2 single-ended reference inputs

Accepts CMOS, LVDS, or LVPECL references to 250 MHz

Accepts 16.62 MHz to 33.3 MHz crystal for reference input

Optional reference clock doubler

Reference monitoring capability

Automatic/ manual reference holdover and reference

switchover modes, with revertive switching

Glitch-free switchover between references

Automatic recovery from holdover

Digital or analog lock detect, selectable

Optional zero delay operation

Twelve 1.6 GHz LVPECL outputs divided into 4 groups

Each group of 3 outputs shares a 1-to-32 divider with

phase delay

Additive output jitter as low as 225 fs rms

Channel-to-channel skew grouped outputs < 16 ps

Each LVPECL output can be configured as 2 CMOS outputs

(for f

OUT

≤ 250 MHz)

Automatic synchronization of all outputs on power-up

Manual output synchronization available

SPI- and I²C-compatible serial control port

64-lead LFCSP

Nonvolatile EEPROM stores configuration settings

APPLICATIONS

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10GFC,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

ATE and high performance instrumentation

Broadband infrastructures

GENERAL DESCRIPTION

The AD9520-5

provides a multioutput clock distribution

function with subpicosecond jitter performance, along with

an on-chip PLL that can be used with an external VCO.

The AD9520 serial interface supports both SPI and I²C ports.

An in-package EEPROM, which can be programmed through the

serial interface, can store user-defined register settings for

power-up and chip reset.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

The AD9520 features 12 LVPECL outputs in four groups. Any

of the 1.6 GHz LVPECL outputs can be reconfigured as two

250 MHz CMOS outputs. If an application requires LVDS

drivers instead of LVPECL drivers, refer to the AD9522.

Each group of three outputs has a divider that allows both the

divide ratio (from 1 to 32) and the phase offset or coarse time

delay to be set.

The AD9520 is

available in a 64-lead LFCSP and can be operated

from a single 3.3 V supply. The external VCO can have an

operating voltage of up to 5.5 V. A separate output driver power

supply can be from 2.375 V to 3.465 V.

The AD9520 is specified for operation over the standard industrial

range of −40°C to +85°C.

AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-5 is used, it refers to that specific member of the

AD9520 family.

REF1

REF2

CLK

SWITCHOVER

AND MONITOR

PLL

DIVIDER

AND MUXES

ZERO

DELAY

STATUS

MONITOR

SPI/I

C CONTROL

PORT AND

DIGITAL LOGIC

EEPROM

AD9520-5

OUT0

OUT1

OUT2

DIV/Φ

OUT3

OUT4

OUT5

DIV/Φ

OUT6

OUT7

OUT8

DIV/Φ

OUT9

OUT10

OUT11

DIV/Φ

LVPECL/

CMOS

REFIN

CLK

07239-001

Summary of content (76 pages)

PAGE 1
2 LVPECL/24 CMOS Output Clock Generator AD9520-5 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM CP REFIN REF2 CLK CLK DIVIDER AND MUXES ZERO DELAY LVPECL/ CMOS DIV/Φ OUT0 OUT1 OUT2 DIV/Φ OUT3 OUT4 OUT5 DIV/Φ OUT6 OUT7 OUT8 DIV/Φ OUT9 OUT10 OUT11 SPI/I2C CONTROL PORT AND DIGITAL LOGIC EEPROM AD9520-5 07239-001 REFIN STATUS MONITOR PLL REF1 SWITCHOVER AND MONITOR Low phase noise, phase-locked loop (PLL) Optional external 3.3 V/5 V VCO/VCXO to 2.
PAGE 2
AD9520-5 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Detailed Block Diagram ................................................................ 25 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 26 General Description ......................................................
PAGE 3
Data Sheet AD9520-5 REVISION HISTORY 8/13—Rev. 0 to Rev. A Changes to Features Section, Applications Section, and General Description Section ............................................................ 1 Changes to Table 2 ............................................................................ 4 Changes to Input Frequency Parameter; Change to Input Sensitivity, Differential Parameter Test Conditions/Comments, Table 3 ...................................................................................
PAGE 4
AD9520-5 Data Sheet SPECIFICATIONS Typical is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter POWER PINS VS VS_DRV VCP CURRENT SET RESISTORS RSET Pin Resistor CPRSET Pin Resistor Min Typ Max Unit Test Conditions/Comments 3.135 2.375 VS 3.3 3.465 VS 5.25 V V V 3.3 V ± 5% Nominally 2.5 V to 3.
PAGE 5
Data Sheet Parameter PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency AD9520-5 Max Unit Test Conditions/Comments 100 45 50 Antibacklash pulse width = 1.3 ns Antibacklash pulse width = 2.9 ns 1.3 2.9 6.0 MHz MHz MHz ns ns ns ICP Sink/Source High Value 4.8 mA Low Value 0.60 mA Reference Input Clock Doubler Frequency Antibacklash Pulse Width Min Typ 0.004 CHARGE PUMP (CP) Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. VCP ICP vs.
PAGE 6
AD9520-5 Parameter PHASE OFFSET IN ZERO DELAY Phase Offset (REF-to-LVPECL Clock Output Pins) in Zero Delay Mode Phase Offset (REF-to-LVPECL Clock Output Pins) in Zero Delay Mode NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector 2 500 kHz PFD Frequency 1 MHz PFD Frequency 10 MHz PFD Frequency 50 MHz PFD Frequency PLL Figure of Merit (FOM) Data Sheet Min Typ Max Unit 560 1060 1310 ps Test Conditions/Comments REF refers to REFIN (REF1)/REFIN (REF2) When N delay and
PAGE 7
Data Sheet AD9520-5 CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min Max Unit 01 01 2.4 2.0 GHz GHz 01 1.6 GHz Input Sensitivity, Differential Typ 150 Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance 1 1.3 1.3 3.9 1.57 150 4.7 2 mV p-p 2 V p-p 1.8 1.8 V V mV p-p kΩ pF 5.
PAGE 8
AD9520-5 Parameter Source Current Static Dynamic Sink Current Static Dynamic Data Sheet Min Typ Max Unit Test Conditions/Comments Damage to the part can result if values are exceeded 20 16 mA mA 8 16 mA mA Typ Max Unit 130 170 ps 130 170 ps 1050 970 1.0 1280 1180 ps ps ps/°C 5 5 5 5 16 20 45 60 190 ps ps ps ps ps 750 715 965 890 960 890 1280 1100 ps ps ps ps 2.75 3.35 2 3.55 ns ns ps/°C VS_DRV = 3.3 V VS_DRV = 2.5 V VS_DRV = 3.3 V and 2.
PAGE 9
Data Sheet AD9520-5 Timing Diagrams DIFFERENTIAL SINGLE-ENDED 80% 80% LVPECL CMOS 10pF LOAD 20% tFP tRC Figure 2. LVPECL Timing, Differential Figure 4. CMOS Timing, Single-Ended, 10 pF Load tCLK CLK 07239-060 tPECL tCMOS tFC Figure 3. CLK/CLK to Clock Output Timing, DIV = 1 Rev.
PAGE 10
AD9520-5 Data Sheet CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6.
PAGE 11
Data Sheet AD9520-5 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 7. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min LVPECL = 245.76 MHz; PLL LBW = 125 Hz Typ Max 54 77 109 79 114 163 124 176 259 LVPECL = 122.88 MHz; PLL LBW = 125 Hz LVPECL = 61.44 MHz; PLL LBW = 125 Hz Unit fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms Test Conditions/Comments Application example based on a typical setup using an external 245.
PAGE 12
AD9520-5 Data Sheet CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 9. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER Min Typ Max Unit CLK = 1.
PAGE 13
Data Sheet AD9520-5 SERIAL CONTROL PORT—I²C MODE Table 11. Parameter SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage Input Logic 0 Voltage Input Current with an Input Voltage Between 0.1 × VS and 0.9 × VS Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSPIKE SDA (WHEN OUTPUTTING DATA) Output Logic 0 Voltage at 3 mA Sink Current Output Fall Time from VIHMIN to VILMAX with a Bus Capacitance from 10 pF to 400 pF TIMING Min Typ Unit 0.
PAGE 14
AD9520-5 Data Sheet PD, SYNC, EEPROM, AND RESET PINS Table 12. Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming SYNC TIMING Pulse Width Low Min Typ Max Unit 0.8 1 −110 V V µA µA 2 pF 2.0 500 100 ns ns 1.
PAGE 15
Data Sheet AD9520-5 POWER DISSIPATION Table 15. Parameter POWER DISSIPATION, CHIP Typ Max Unit 1.32 0.39 1.5 0.46 W W 0.36 0.42 W 1.4 1.7 W PD Power-Down 60 80 mW PD Power-Down, Maximum Sleep 24 33 mW 4 4.
PAGE 16
AD9520-5 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 16.
PAGE 17
Data Sheet AD9520-5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 REFIN (REF1) REFIN (REF2) CPRSET VS VS GND RSET VS OUT0 (OUT0A) OUT0 (OUT0B) VS_DRV OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) VS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9520-5 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OUT3 (OUT3A) OUT3 (OUT3B) VS_DRV OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) VS VS OUT8 (OUT8B) OUT8 (OUT8A)
PAGE 18
AD9520-5 Data Sheet Pin No. 15 Input/ Output I Pin Type 3.3 V CMOS Mnemonic CS 16 I 3.3 V CMOS SCLK/SCL 17 18 19, 59 20 I/O O I I SDIO/SDA SDO GND SP1 21 I 22 I 3.3 V CMOS 3.3 V CMOS GND Three-level logic Three-level logic 3.3 V CMOS 23 24 25 I I O RESET PD OUT9 (OUT9A) 26 O 27, 35, 46, 54 28 I 3.3 V CMOS 3.
PAGE 19
Data Sheet Pin No.
PAGE 20
AD9520-5 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 350 5 3 CHANNELS—6 LVPECL 3 CHANNELS—3 LVPECL 250 2 CHANNELS—2 LVPECL 200 4 CURRENT FROM CP PIN (mA) CURRENT (mA) 300 150 PUMP DOWN PUMP UP 3 2 1 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) 0 07239-108 100 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOLTAGE ON CP PIN (V) Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off), LVPECL Outputs Terminated 50 Ω to VS_DRV − 2 V Figure 9.
PAGE 21
Data Sheet AD9520-5 3.5 3.2 VS_DRV = 3.3V 2.8 3.0 VS_DRV = 3.135V 2.4 AMPLITUDE (V) 1.5 2.0 1.6 1.2 1.0 0.8 0.5 0.4 0 0 10k 1k 100 RESISTIVE LOAD (Ω) 0 07239-118 VOH (V) VS_DRV = 2.35V 2.0 10 20 30 40 50 60 70 80 90 100 TIME (ns) 07239-018 VS_DRV = 2.5V 2.5 Figure 15. CMOS Output with 10 pF Load at 25 MHz Figure 12. CMOS Output VOH (Static) vs. RLOAD (to Ground) 1.2 2pF LOAD 3.2 2.8 10pF LOAD 2.4 0.4 AMPLITUDE (V) DIFFERENTIAL OUTPUT (V) 0.8 0 –0.4 2.0 1.6 1.
PAGE 22
AD9520-5 Data Sheet 4.0 –100 3.5 –110 PHASE NOISE (dBc/Hz) 3.0 AMPLITUDE (V) 2pF 2.5 2.0 10pF 1.5 20pF 1.0 –120 –130 –140 –150 100 200 300 400 500 600 700 FREQUENCY (MHz) Figure 18. CMOS Output Swing vs. Frequency and Capacitive Load 1k 10k 100k 1M 10M 100M Figure 20.
PAGE 23
Data Sheet AD9520-5 –110 –120 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –120 –130 –140 –150 –130 –140 –150 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) –160 1k Figure 22. Additive (Residual) Phase Noise, CLK-to-CMOS at 50 MHz, Divide-by-20 INPUT JITTER AMPLITUDE (UI p-p) –120 –130 –140 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 07239-132 –150 1M 10M 100M Figure 24. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) at 245.76 MHz; PFD = 15.
PAGE 24
AD9520-5 Data Sheet TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.
PAGE 25
Data Sheet AD9520-5 DETAILED BLOCK DIAGRAM VS REFMON RSET GND DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0
PAGE 26
AD9520-5 Data Sheet THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9520 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 44 to Table 55). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers.
PAGE 27
Data Sheet AD9520-5 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0 OUT1 OUT1 DIGITAL LOGI
PAGE 28
AD9520-5 Data Sheet Mode 2—High Frequency Clock Distribution; CLK or External VCO > 1600 MHz When using the internal PLL with an external VCO, the PLL must be turned on. The AD9520 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6).
PAGE 29
Data Sheet AD9520-5 VS RSET GND REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 VS_DRV CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0 OUT1 OUT1 DIGITAL LOGI
PAGE 30
AD9520-5 Data Sheet Phase-Locked Loop (PLL) VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF REFIN LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD STATUS AMP P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK VS_DRV FROM CHANNEL DIVIDER 0 1 07239-064 CLK 0 F
PAGE 31
Data Sheet AD9520-5 PLL External Loop Filter An example of an external loop filter for the PLL is shown in Figure 30. The external loop filter should be referenced to ground. A loop filter must be calculated for each desired PLL configuration. The component values depend upon the VCO frequency, the KVCO, the PFD frequency, the CP current, the desired loop bandwidth, and the desired phase margin. The loop filter affects the phase noise, loop settling time, and loop stability.
PAGE 32
AD9520-5 Data Sheet The AD9520 features a dc offset option in single-ended mode. This option is designed to eliminate the risk of the reference inputs chattering when they are ac-coupled and the reference clock disappears. When using the reference switchover, the singleended reference inputs should be dc-coupled CMOS levels (with the AD9520 dc offset feature disabled). Alternatively, the inputs can be ac-coupled and dc offset feature enabled.
PAGE 33
Data Sheet AD9520-5 Table 25.
PAGE 34
AD9520-5 Data Sheet The analog lock detect function requires an RC filter to provide a logic level indicating lock/unlock. The ADIsimCLK tool can be used to help the user select the right passive component values for ALD to ensure its correct operation. External VCXO/VCO Clock Input (CLK/CLK) VS = 3.3V R2 LD ALD This differential input is used to drive the AD9520 clock distribution section. This input can receive up to 2.4 GHz.
PAGE 35
Data Sheet AD9520-5 The B counter (in the N divider) is reset synchronously with the charge pump, leaving the high impedance state on the reference path PFD event. This helps align the edges out of the R and N dividers for faster settling of the PLL. Because the prescaler is not reset, this feature works best when the B and R numbers are close, resulting in a smaller phase difference for the loop to settle out.
PAGE 36
AD9520-5 Data Sheet The following registers affect the automatic/internal holdover function: The following registers are set (in addition to the normal PLL registers): • • • Register 0x018[6:5]—lock detect counter. This changes how many consecutive PFD cycles with edges inside the lock detect window are required for the DLD indicator to indicate lock.
PAGE 37
Data Sheet AD9520-5 EXTERNAL VCXO REFIN/ REFIN R DIVIDER AD9520-5 R DELAY PFD N DIVIDER LOOP FILTER CP N DELAY REG 0x01E[1] = 1 MUX1 INTERNAL ZERO DELAY CLOCK FEEDBACK PATH DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK/CLK CHANNEL DIVIDER 0 OUT0 TO OUT2 CHANNEL DIVIDER 1 OUT3 TO OUT5 CHANNEL DIVIDER 2 OUT6 TO OUT8 CHANNEL DIVIDER 3 OUT9 TO OUT11 0 07239-053 1 Figure 37.
PAGE 38
AD9520-5 Data Sheet PLL DIVIDE BY 1, 2, 3, 4, 5, OR 6 DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK CLK 1 0 DISTRIBUTION CLOCK 1 CLOCK DISTRIBUTION MODE 1 (CLOCK DISTRIBUTION MODE) 0 DISTRIBUTION CLOCK CLOCK DISTRIBUTION MODE 2 (HF CLOCK DISTRIBUTION MODE) 07239-054 CLK PLL Figure 38. Simplified Diagram of the Two Clock Distribution Operation Modes CLOCK DISTRIBUTION A clock channel consists of three LVPECL clock outputs or six CMOS clock outputs that share a common divider.
PAGE 39
Data Sheet AD9520-5 Clock Frequency Division The total frequency division is a combination of the VCO divider (when used) and the channel divider. When the VCO divider is used, the total division from the CLK to the output is the product of the VCO divider (1, 2, 3, 4, 5, and 6) and the division of the channel divider. Table 28 shows how the frequency division for a channel is set. Table 28.
PAGE 40
AD9520-5 Data Sheet Duty-cycle correction requires the following channel divider conditions: • • An even division must be set as M = N. An odd division must be set as M = N + 1. When not bypassed or corrected by the DCC function, the duty cycle of each channel divider output is the numerical value of (N + 1)/(N + M + 2), expressed as a percent. Table 30 to Table 33 show the output duty cycle for various configurations of the channel divider and VCO divider. Table 30.
PAGE 41
Data Sheet AD9520-5 0 Each channel divider allows for a phase offset, or a coarse time delay, to be programmed by setting register bits (see Table 34). These settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset, or delay, the rising edge of the output of the divider. This delay is with respect to a nondelayed output (that is, with a phase offset of zero).
PAGE 42
AD9520-5 Data Sheet The AD9520 differential LVPECL outputs are four groups of three, sharing a channel divider per triplet. In the case of CMOS, each LVPECL differential pair can be configured as two singleended CMOS outputs. The synchronization conditions apply to all of the drivers that belong to that channel divider. Another common way to execute the SYNC function is by setting and resetting the soft SYNC bit at Register 0x230[0].
PAGE 43
Data Sheet AD9520-5 The LVPECL differential voltage (VOD) is selectable (from ~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to Register 0x0FB). The LVPECL outputs have dedicated pins for power supply (VS_DRV), allowing a separate power supply to be used. VS_DRV can be set to either 2.5 V or 3.3 V. The LVPECL output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change.
PAGE 44
AD9520-5 Data Sheet Soft Reset via the Serial Port • The serial port control register allows for a soft reset by setting Bit 2 and Bit 5 in Register 0x000. The function of this register is determined by the state of the EEPROM pin. • When Bit 2 and Bit 5 are set and the EEPROM pin is high, the chip is restored to the settings saved in the EEPROM. When Bit 2 and Bit 5 are set and the EEPROM pin is low, the chip is restored to the on-chip defaults.
PAGE 45
Data Sheet AD9520-5 SERIAL CONTROL PORT SPI/I²C PORT SELECTION Table 35. Serial Port Mode Selection DATA LINE STABLE; DATA VALID Address I²C, 1011000b I²C, 1011001b I²C, 1011010b I²C, 1011011b I²C, 1011100b I²C, 1011101b I²C, 1011110b I²C, 1011111b SPI SDA Figure 44. Valid Bit Transfer A start condition is a transition from high to low on the SDA line while SCL is high. The start condition is always generated by the master to initialize the data transfer.
PAGE 46
AD9520-5 MSB 2 3 TO 7 8 9 1 2 3 TO 7 8 9 S 10 P 07239-162 1 SCL ACKNOWLEDGE FROM SLAVE-RECEIVER 10 P 07239-163 ACKNOWLEDGE FROM SLAVE-RECEIVER 10 P 07239-164 SDA Data Sheet Figure 46. Acknowledge Bit SDA MSB = 0 ACKNOWLEDGE FROM SLAVE-RECEIVER 1 SCL 2 3 TO 7 8 9 1 ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 9 8 S Figure 47.
PAGE 47
Data Sheet AD9520-5 Data Transfer Format Send byte format—the send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A RAM Address High Byte A RAM Address Low Byte A P Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
PAGE 48
AD9520-5 Data Sheet SPI SERIAL PORT OPERATION Pin Descriptions SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and the read data bits transition on the falling edge of SCLK. This pin is internally pulled down by a 30 kΩ resistor to ground.
PAGE 49
Data Sheet AD9520-5 SPI MSB/LSB FIRST TRANSFERS The default mode of the AD9520 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin. It is also possible to set the AD9520 to unidirectional mode (Register 0x000[7] = 1b and Register 0x000[0] = 1b). In unidirectional mode, the readback data appears on the SDO pin. The AD9520 uses Register 0x000 to Register 0xB03. The default for the AD9520 is MSB first.
PAGE 50
AD9520-5 Data Sheet CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 07239-038 DON'T CARE Figure 52.
PAGE 51
Data Sheet AD9520-5 tC tS CS tCLK tLOW tHIGH SCLK tDS SDIO BIT N BIT N + 1 07239-043 tDH Figure 57. Serial Control Port Timing—Write Table 41.
PAGE 52
AD9520-5 Data Sheet EEPROM OPERATIONS The AD9520 contains an internal EEPROM (nonvolatile memory). The EEPROM can be programmed by users to create and store a user-defined register setting file when the power is off. This setting file can be used for power-up and chip reset as a default setting. The EEPROM size is 512 bytes. Note that to guarantee proper loading of the EEPROM during startup, a high-low-high pulse on the RESET pin should occur after the power supply has stabilized.
PAGE 53
Data Sheet AD9520-5 PROGRAMMING THE EEPROM BUFFER SEGMENT IO_UPDATE (Operational Code 0x80) The EEPROM buffer segment is a register space on the AD9520. The user can specify which groups of registers are stored to the EEPROM during EEPROM programming. Note that programming this register space is optional. The default power-up values for the EEPROM buffer segment allow storage of all the AD9520 register values from Register 0x000 to Register 0x231 to the EEPROM.
PAGE 54
AD9520-5 Data Sheet THERMAL PERFORMANCE Table 43. Thermal Parameters for 64-Lead LFCSP Symbol θJA θJMA θJMA ΨJB θJC ΨJT Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
PAGE 55
Data Sheet AD9520-5 REGISTER MAP Register addresses that are not listed in Table 44 are not used, and writing to those registers has no effect. Writing to register addresses that are marked as unused also has no effect. Table 44. Register Map Overview Addr.
PAGE 56
AD9520-5 Data Sheet Addr.
PAGE 57
Data Sheet AD9520-5 Addr.
PAGE 58
AD9520-5 Data Sheet REGISTER MAP DESCRIPTIONS Table 45 to Table 55 provide a detailed description of each of the control register functions. Table 45. SPI Mode Serial Port Configuration Reg. Addr. (Hex) 0x000 Bits 7 Name SDO active 6 LSB first/addr incr 5 Soft reset 4 [3:0] Unused Mirror[7:4] 0x003 [7:0] Part ID (read only) 0x004 0x004 [7:1] 0 Unused Read back active registers Description Selects unidirectional or bidirectional data transfer mode.
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Data Sheet AD9520-5 Table 48. PLL Reg. Addr. (Hex) 0x010 Bits 7 Name PFD polarity [6:4] CP current [3:2] CP mode [1:0] 0x011 [7:0] 0x012 [7:6] [5:0] 0x013 [7:6] [5:0] [7:0] 0x014 0x015 [7:5] [4:0] 0x016 7 6 5 4 3 Description Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO. 0: positive (higher control voltage produces higher frequency) (default). 1: negative (higher control voltage produces lower frequency). Charge pump current (with CPRSET = 5.
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AD9520-5 Reg. Addr. (Hex) 0x017 Bits [2:0] Name Prescaler P [7:2] STATUS pin control Data Sheet Description Prescaler: DM = dual modulus and FD = fixed divide. The Prescaler P is part of the feedback divider. Bit Bit Bit 2 1 0 Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0. 0 1 1 DM Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0. 1 0 0 DM Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.
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Data Sheet Reg. Addr. (Hex) 0x018 0x019 Bits [1:0] Name Antibacklash pulse width 7 Enable CMOS reference input dc offset [6:5] Lock detect counter 4 Digital lock detect window 3 Disable digital lock detect [2:0] [7:6] Unused R, A, B counters SYNC pin reset AD9520-5 Description Bit Bit 1 0 Antibacklash Pulse Width (ns) 0 0 2.9 (default) 0 1 1.3 1 0 6.0 1 1 2.9 Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost.
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AD9520-5 Reg. Addr. (Hex) Data Sheet Bits Name [5:0] LD pin control 0x01B 7 6 5 Description Selects the signal that is connected to the LD pin. Level or Bit Bit Bit Bit Bit Bit Dynamic 5 4 3 2 1 0 Signal Signal at LD Pin 0 0 0 0 0 0 LVL Digital lock detect (high = lock; low = unlock, default). 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 1 HIZ Tristate (high-Z) LD pin.
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Data Sheet Reg. Addr. (Hex) Bits [4:0] 0x01C 7 6 5 4 3 2 1 0 AD9520-5 Name Description REFMON pin Selects the signal that is connected to the REFMON pin. control Level or Bit Bit Bit Bit Bit Dynamic 4 3 2 1 0 Signal Signal at REFMON Pin 0 0 0 0 0 LVL Ground, dc (default). 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode).
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AD9520-5 Reg. Addr. (Hex) Bits 0x01D 7 Name Enable STATUS_ EEPROM at STATUS pin Enable XTAL OSC Description Enables the STATUS_EEPROM signal at the STATUS pin. 0: the STATUS pin is controlled by the Register 0x017[7:2] selection. 1: selects the STATUS_EEPROM signal at the STATUS pin. This bit overrides the Reigster 0x017[7:2] selection (default).
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Data Sheet AD9520-5 Table 49. Output Driver Control Reg Addr (Hex) Bits 0x0F0 7 [6:5] [4:3] [2:1] 0 0x0F1 0x0F2 0x0F3 0x0F4 0x0F5 0x0F6 0x0F7 0x0F8 0x0F9 0x0FA 0x0FB 0x0FC [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 7 6 5 4 3 2 1 0 0x0FD [7:4] 3 2 1 0 Name OUT0 format Description Selects the output type for OUT0. 0: LVPECL (default). 1: CMOS. OUT0 CMOS Sets the CMOS output configuration for OUT0 when Register 0x0F0[7] = 1.
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AD9520-5 Data Sheet Table 50. LVPECL Channel Dividers Reg. Addr.
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Data Sheet Reg. Addr.
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AD9520-5 Reg. Addr. (Hex) Bits 5 4 [3:0] 0x19B [7:3] 2 Name Divider 3 force high Divider 3 start high Divider 3 phase offset Unused Channel 3 power-down 1 Channel 3 direct-to-output 0 Disable Divider 3 DCC Data Sheet Description Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit has no effect if the channel divider is bypassed, but the driver polarity can still be reversed. 0: divider output is forced to low (default).
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Data Sheet AD9520-5 Table 52. System Reg. Addr. (Hex) Bits 0x230 [7:4] 3 2 1 0 Name Unused Disable power on SYNC Description Unused. Powers on SYNC mode. Used to disable the antiruntpulse circuitry. 0: enables the antiruntpulse circuitry (default). 1: disables the antiruntpulse circuitry. Power down SYNC Powers down the SYNC function. 0: normal operation of the SYNC function (default). 1: powers down SYNC circuitry. Power down distribution Powers down the reference for the distribution section.
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AD9520-5 Data Sheet Table 55. EEPROM Control Reg. Addr. (Hex) Bits Name 0xB00 [7:1] Unused 0 STATUS_EEPROM (read only) Description Unused. This read-only register indicates the status of the data transfer between the EEPROM and the buffer register bank during the writing and reading of the EEPROM. This signal is also available at the STATUS pin when Register 0x01D[7] is set. 0: data transfer is complete. 1: data transfer is not complete. 0xB01 [7:1] Unused Unused.
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Data Sheet AD9520-5 APPLICATIONS INFORMATION When determining a starting point, choosing a nominal charge pump current in the middle of the allowable range allows the designer to increase or decrease the charge pump current and, thus, allows fine-tuning of the PLL loop bandwidth in either direction. Analog Devices, Inc., has an AD9520 configuration tool that can determine the best PLL configuration, based on the user’s input and output frequencies.
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AD9520-5 Data Sheet LVPECL CLOCK DISTRIBUTION Far-End Thevenin Termination The LVPECL outputs of the AD9520 provide the lowest jitter clock signals available from the AD9520. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 42 shows the LVPECL output stage. Far-end Thevenin termination uses a resistor network to provide 50 Ω termination to a dc voltage that is below VOL of the LVPECL driver.
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Data Sheet AD9520-5 Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9520 do not supply enough current to provide a full voltage swing with a low impedance resistive, farend termination, as shown in Figure 63. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications.
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AD9520-5 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.25 0.18 0.60 MAX 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 16 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-12-2012-B 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.
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Data Sheet AD9520-5 NOTES Rev.
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AD9520-5 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07239-0-8/13(A) Rev.