2 LVDS/24 CMOS Output Clock Generator with Integrated 2.4 GHz VCO AD9522-1 APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.
AD9522-1 TABLE OF CONTENTS Features .............................................................................................. 1 Operational Configurations ...................................................... 27 Applications ....................................................................................... 1 Mode 0: Internal VCO and Clock Distribution ................. 27 General Description .........................................................................
AD9522-1 Reset Modes .................................................................................48 EEPROM Operations ..................................................................... 57 Power-On Reset.......................................................................48 Writing to the EEPROM ............................................................ 57 Hardware Reset via the RESET Pin ......................................48 Reading from the EEPROM .......................................
AD9522-1 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter VS VCP RSET Pin Resistor CPRSET Pin Resistor Min 3.135 VS BYPASS Pin Capacitor Typ 3.3 Max 3.465 5.25 4.12 5.1 Unit V V kΩ kΩ 220 nF Test Conditions/Comments 3.3 V ± 5% This is nominally 3.3 V to 5.
AD9522-1 Parameter Crystal Oscillator Crystal Resonator Frequency Range Maximum Crystal Motional Resistance PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency Max Unit 33.33 30 MHz Ω 100 45 50 1.3 2.9 6.0 MHz MHz MHz ns ns ns CHARGE PUMP (CP) ICP Sink/Source High Value 4.8 mA Low Value 0.6 mA Reference Input Clock Doubler Frequency Antibacklash Pulse Width Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. VCP ICP vs.
AD9522-1 Parameter PHASE OFFSET IN ZERO DELAY Phase Offset (REF-to-LVDS Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-LVDS Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) @ 500 kHz PFD Frequency @ 1 MHz PFD Frequency @ 10 MHz PFD Fr
AD9522-1 CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min Typ 01 01 Input Sensitivity, Differential 1 Unit 2.4 1.6 GHz GHz 150 Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Max 1.3 1.3 3.9 1.57 150 4.7 2 mV p-p 2 V p-p 1.8 1.8 V V mV p-p kΩ pF 5.
AD9522-1 TIMING CHARACTERISTICS Table 5.
AD9522-1 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter CLK-TO-LVDS ADDITIVE PHASE NOISE CLK = 1.
AD9522-1 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter LVDS ABSOLUTE PHASE NOISE Min VCO = 2650 MHz; Output = 662.5 MHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset VCO = 2460 MHz; Output = 615 MHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset VCO = 2270 MHz; Output = 567.
AD9522-1 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter LVDS OUTPUT ABSOLUTE TIME JITTER Min LVDS = 245.76 MHz; PLL LBW = 125 Hz Typ Max 87 108 146 120 151 207 157 210 295 LVDS = 122.88 MHz; PLL LBW = 125 Hz LVDS = 61.44 MHz; PLL LBW = 125 Hz Unit fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms Test Conditions/Comments Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.
AD9522-1 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 12.
AD9522-1 SERIAL CONTROL PORT—I²C MODE Table 14. Parameter SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage Input Logic 0 Voltage Input Current with an Input Voltage Between 0.1 × VS and 0.
AD9522-1 PD, SYNC, AND RESET PINS Table 15. Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Min Typ Max Unit 0.8 1 −110 V V μA μA 2 pF 2.0 Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming 50 100 ns ns SYNC TIMING Pulse Width Low 1.
AD9522-1 POWER DISSIPATION Table 18. Parameter POWER DISSIPATION, CHIP Typ Max Unit Power-On Default PLL Locked; One LVDS Output Enabled 0.88 0.54 1.0 0.63 W W PLL Locked; One CMOS Output Enabled 0.55 0.66 W Distribution Only Mode; VCO Divider On; One LVDS Output Enabled Distribution Only Mode; VCO Divider Off; One LVDS Output Enabled Maximum Power, Full Operation 0.36 0.43 W 0.33 0.4 W 1.1 1.3 W PD Power-Down 35 50 mW PD Power-Down, Maximum Sleep 27 43 mW 8 2.
AD9522-1 ABSOLUTE MAXIMUM RATINGS Table 19. Parameter or Pin VS VCP, CP REFIN, REFIN RSET, LF, BYPASS CPRSET CLK, CLK CLK SCLK/SCL, SDIO/SDA, SDO, CS OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, OUT9, OUT9, OUT10, OUT10, OUT11, OUT11 SYNC, RESET, PD REFMON, STATUS, LD SP0, SP1, EEPROM Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec) 1 With Respect to GND GND GND GND GND GND CLK GND GND Rating −0.3 V to +3.6 V −0.
AD9522-1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 REFIN (REF1) REFIN (REF2) CPRSET VS VS GND RSET VS OUT0 (OUT0A) OUT0 (OUT0B) VS OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) VS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9522 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OUT3 (OUT3A) OUT3 (OUT3B) VS OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) VS VS OUT8 (OUT8B) OUT8 (OUT8A) OUT7 (OUT7B) OUT7 (OU
AD9522-1 Pin No. 15 Input/ Output I Pin Type 3.3 V CMOS Mnemonic CS 16 I 3.3 V CMOS SCLK/SCL 17 18 19, 59 20 I/O O I I SDIO/SDA SDO GND SP1 21 I 22 I 3.3 V CMOS 3.3 V CMOS GND Three-level logic Three-level logic 3.3 V CMOS 23 24 25 I I O RESET PD OUT9 (OUT9A) 26 O 28 O 29 O 30 O 31 O 33 O 34 O 36 O 37 O 38 O 39 O 42 O 43 O 44 O 45 O 3.3 V CMOS 3.
AD9522-1 Pin No. 47 Input/ Output O 48 O 50 O 51 O 52 O 53 O 55 O 56 O 58 O 62 O 63 I 64 I EPAD Pin Type LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS Current set resistor Current set resistor Reference input Reference input GND Mnemonic OUT3 (OUT3B) OUT3 (OUT3A) OUT2 (OUT2B) OUT2 (OUT2A) OUT1 (OUT1B) OUT1 (OUT1A) OUT0 (OUT0B) OUT0 (OUT0A) RSET CPRSET REFIN (REF2) REFIN (REF1) GND Description Clock Output.
AD9522-1 TYPICAL PERFORMANCE CHARACTERISTICS 275 5 3 CHANNELS—6 LVDS CURRENT FROM CP PIN (mA) 250 3 CHANNELS—3 LVDS 200 175 2 CHANNELS—2 LVDS 150 125 4 PUMP DOWN PUMP UP 3 2 1 1 CHANNEL—1 LVDS 75 0 200 400 600 800 1000 FREQUENCY (MHz) 0 07220-108 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V) Figure 6. Total Current vs.
AD9522-1 –208 0 –10 –20 –212 –30 –214 POWER (dBm) PLL FIGURE OF MERIT (dBc/Hz) –210 –216 –218 –40 –50 –60 DIFFERENTIAL INPUT –70 –220 –80 –222 –90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 INPUT SLEW RATE (V/ns) –100 122.38 07220-114 –224 122.58 122.78 122.98 123.18 123.38 FREQUENCY (MHz) Figure 12. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN 07220-117 SINGLE-ENDED INPUT Figure 15. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.
0.4 1600 0.3 1400 DIFFERENTIAL SWING (mV p-p) 0.2 0.1 0 –0.1 –0.2 1000 800 DEFAULT 3.5mA SETTING 600 400 –0.3 0.5 1.0 1.5 2.0 3.0 2.5 TIME (ns) 0 07220-015 0 0 400 600 800 1000 FREQUENCY (GHz) Figure 18. LVDS Differential Voltage Swing @ 800 MHz, Output Terminated 100 Ω Across Differential Pair Figure 21. LVDS Differential Voltage Swing vs. Frequency, Output Terminated 100 Ω Across Differential Pair 4.0 3.2 2.8 3.5 2.4 3.0 2pF AMPLITUDE (V) 2.0 1.6 1.2 0.8 2.5 2.0 10pF 1.
AD9522-1 –50 –100 –60 –110 –80 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –70 –90 –100 –110 –120 –130 –140 –120 –130 –140 –150 10k 100k 1M 10M 100M FREQUENCY (Hz) –160 10 07220-024 –160 1k 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 24. Internal VCO Phase Noise (Absolute), LVDS Output @ 615 MHz 07220-129 –150 Figure 27.
AD9522-1 –100 –80 INTEGRATED RMS JITTER (12kHz TO 20MHz): 146fs –90 PHASE NOISE (dBc/Hz) –120 –130 –140 –150 –110 –120 –130 –140 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) –160 1k Figure 30. Additive (Residual) Phase Noise, CLK-to-CMOS @ 250 MHz, Divide-by-4 10k 100k R2 390Ω CP C2 62pF C1 240nF R1 820Ω LF C3 33pF BYPASS –120 BYPASS CAPACITOR FOR LDO –130 R2 3kΩ CP –150 10k 100k 1M 10M 100M 07220-033 C2 1.
AD9522-1 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as Gaussian (normal) in distribution.
AD9522-1 DETAILED BLOCK DIAGRAM VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK OUT0 CLK OUT0 1 DIVIDE B
AD9522-1 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS Table 22. Settings When Using Internal VCO The AD9522 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 48 to Table 59). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers.
AD9522-1 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK OUT0 CLK 1 DIVIDE BY 1 TO 32 PD SYNC OUT0 0
AD9522-1 Mode 1: Clock Distribution or External VCO < 1600 MHz When the external clock source to be distributed or the external VCO/VCXO is <1600 MHz, a configuration that bypasses the VCO divider can be used. This is the only difference from Mode 2. Bypassing the VCO divider limits the frequency of the clock source to <1600 MHz (due to the maximum input frequency allowed at the channel dividers).
AD9522-1 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0
AD9522-1 Mode 2: High Frequency Clock Distribution—CLK or External VCO > 1600 MHz Table 26. Default Register Settings for Clock Distribution Mode The AD9522 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6). This is a distribution-only mode that allows for an external input up to 2400 MHz (see Table 3).
AD9522-1 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP BYPASS STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0
AD9522-1 Phase-Locked Loop (PLL) VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF REFIN BYPASS LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD STATUS LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK FROM CHANNEL DIVIDER 0 1 0722
AD9522-1 Charge Pump (CP) AD9522 LF VCO CHARGE PUMP The on-chip VCO is powered by an on-chip, low dropout (LDO), linear voltage regulator. The LDO provides some isolation of the VCO from variations in the power supply voltage level. The BYPASS pin should be connected to ground by a 220 nF capacitor to ensure stability. This LDO employs the same technology used in the anyCAP® line of regulators from Analog Devices, Inc., making it insensitive to the type of capacitor used.
AD9522-1 The differential reference input receiver is powered down when it is not selected or when the PLL is powered down. The singleended buffers power down when the PLL is powered down or when their respective individual power-down registers are set. When the differential mode is selected, the single-ended inputs are powered down. In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible to dc couple to these inputs.
AD9522-1 Prescaler The prescaler of the AD9522 allows for two modes of operation: a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM) mode where the prescaler divides by P and (P + 1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of operation are given in Table 52, 0x016[2:0]. Not all modes are available at all frequencies (see Table 2).
AD9522-1 VS = 3.3V Digital Lock Detect (DLD) The lock detect window timing depends on the value of the CPRSET resistor, as well as three settings: the digital lock detect window bit (0x018[4]), the antibacklash pulse width bit (0x017[1:0], see Table 2), and the lock detect counter (0x018[6:5]). The lock and unlock detection values in Table 2 are for the nominal value of CPRSET = 5.11 kΩ. Doubling the CPRSET value to 10 kΩ doubles the values in Table 2.
AD9522-1 External VCXO/VCO Clock Input (CLK/CLK) External/Manual Holdover Mode This differential input is used to drive the AD9522 clock distribution section. This input can receive up to 2.4 GHz. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors. A manual holdover mode can be enabled that allows the user to place the charge pump into a high impedance state when the SYNC pin is asserted low. This operation is edge sensitive, not level sensitive.
AD9522-1 PLL ENABLED LOOP OUT OF LOCK. DIGITAL LOCK DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK AS DETERMINED BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD. NO DLD == LOW YES NO ANALOG LOCK DETECT PIN INDICATES LOCK WAS PREVIOUSLY ACHIEVED. (0x01D[3] = 1; USE LD PIN VOLTAGE WITH HOLDOVER. 0x01D[3] = 0; IGNORE LD PIN VOLTAGE, TREAT LD PIN AS ALWAYS HIGH.) WAS LD PIN == HIGH WHEN DLD WENT LOW? YES CHARGE PUMP IS MADE HIGH IMPEDANCE. PLL COUNTERS CONTINUE OPERATING NORMALLY.
AD9522-1 In the following example, automatic holdover is configured with After leaving holdover, the loop then reacquires lock and the LD pin must go high (if 0x01D[3] = 1) before it can reenter holdover. • • • The holdover function always responds to the state of the currently selected reference (0x01C). If the loop loses lock during a reference switchover (see the Reference Switchover section), holdover is triggered briefly until the next reference clock edge at the PFD.
AD9522-1 VCO Calibration The AD9522 on-chip VCO must be calibrated to ensure proper operation over process and temperature. The VCO calibration is controlled by a calibration controller running off a divided REFIN clock. The calibration requires that the PLL be set up properly to lock the PLL loop and that the REFIN clock be present. The REFIN clock must come from a stable source external to the AD9522. VCO calibration can be performed in two ways: automatically at power-up and manually.
AD9522-1 REFIN/ REFIN R DIVIDER AD9522 R DELAY PFD N DIVIDER LOOP FILTER CP N DELAY REG 0x01E[1] = 1 MUX1 MUX3 INTERNAL FEEDBACK PATH ZERO DELAY FEEDBACK CLOCK LF EXTERNAL FEEDBACK PATH REG 0x01E[2] DIVIDE BY 1, 2, 3, 4, 5, OR 6 ZERO DELAY CLK/CLK CHANNEL DIVIDER 0 OUT0 TO OUT2 CHANNEL DIVIDER 1 OUT3 TO OUT5 CHANNEL DIVIDER 2 OUT6 TO OUT8 CHANNEL DIVIDER 3 OUT9 TO OUT11 0 07220-053 1 Figure 49.
AD9522-1 PLL PLL CLK LF DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK LF DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK 1 CLK 0 DISTRIBUTION CLOCK 1 CLOCK DISTRIBUTION MODE 0 (INTERNAL VCO MODE) DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK 0 DISTRIBUTION CLOCK 1 CLOCK DISTRIBUTION MODE 1 (CLOCK DISTRIBUTION MODE) 0 DISTRIBUTION CLOCK CLOCK DISTRIBUTION MODE 2 (HF CLOCK DISTRIBUTION MODE) 07220-054 LF PLL Figure 50.
AD9522-1 Clock Frequency Division Channel Dividers The total frequency division is a combination of the VCO divider (when used) and the channel divider. When the VCO divider is used, the total division from the VCO or CLK to the output is the product of the VCO divider (1, 2, 3, 4, 5, or 6) and the division of the channel divider. Table 32 indicates how the frequency division for a channel is set. A channel divider drives each group of three LVDS outputs.
AD9522-1 Duty-cycle correction requires the following channel divider conditions: Table 36. Channel Divider Output Duty Cycle When the VCO Divider Is Enabled and Set to 1 • • Input Clock Duty Cycle Any N+M+2 Even 50% Odd The duty cycle at the output of the channel divider for various configurations is shown in Table 34 to Table 37. X% Odd Table 34.
AD9522-1 Let Δt = delay (in seconds). Δc = delay (in cycles of clock signal at input to DX). TX = period of the clock signal at the input of the divider, DX (in seconds). Φ= 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0] Case 1 For Φ ≤ 15, Δt = Φ × TX Δc = Δt/TX = Φ Case 2 For Φ ≥ 16, Δt = (Φ − 16 + M + 1) × TX Δc = Δt/TX By giving each divider a different phase offset, output-to-output delays can be set in increments of the channel divider input clock cycle.
AD9522-1 CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC INPUT TO VCO DIVIDER 1 1 INPUT TO CHANNEL DIVIDER 2 3 4 5 6 7 9 8 11 10 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 07220-073 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT Figure 52.
AD9522-1 CMOS Output Drivers The user can also individually configure each LVDS output as a pair of CMOS outputs, which provides up to 24 CMOS outputs. When an output is configured as CMOS, CMOS Output A and CMOS Output B are automatically turned on. For a given differential pair, either CMOS Output A or Output B can be turned on or off independently. The user can also select the relative polarity of the CMOS outputs for any combination of inverting and noninverting (see Register 0x0F0 to Register 0x0FB).
AD9522-1 PLL Power-Down Individual Clock Output Power-Down The PLL section of the AD9522 can be selectively powered down. There are two PLL power-down modes set by Register 0x010[1:0]: asynchronous and synchronous. Any of the clock distribution outputs can be put into powerdown mode by individually writing to the appropriate registers. The register map details the individual power-down settings for each output. These settings are found in Register 0x0F0[0] to Register 0x0FB[0].
AD9522-1 SERIAL CONTROL PORT The AD9522 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9522 serial control port is compatible with most synchronous transfer formats, including Philips I2C, Motorola® SPI®, and Intel® SSR protocols.
AD9522-1 MSB ACKNOWLEDGE FROM SLAVE-RECEIVER 1 SCL 2 3 TO 7 8 9 1 ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 8 9 S 10 P 07220-162 SDA Figure 58. Acknowledge Bit MSB = 0 1 SCL 2 3 TO 7 8 9 1 ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 8 9 S 10 P 07220-163 ACKNOWLEDGE FROM SLAVE-RECEIVER 10 P 07220-164 SDA Figure 59.
AD9522-1 Data Transfer Format Send byte format—the send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A RAM Address High Byte A RAM Address Low Byte A P Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
AD9522-1 SPI SERIAL PORT OPERATION Pin Descriptions SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 30 kΩ resistor to ground.
AD9522-1 The default mode of the AD9522 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin. It is also possible to set the AD9522 to unidirectional mode (0x000[7] = 1 and 0x000[0] = 1). In unidirectional mode, the readback data appears on the SDO pin. A readback request reads the data that is in the serial control port buffer area or the data that is in the active registers (see Figure 63).
AD9522-1 Table 44. Serial Control Port, 16-Bit Instruction Word, MSB First MSB LSB I15 R/W I14 W1 I13 W0 I12 A12 = 0 I11 A11 = 0 I10 A10 = 0 I9 A9 I8 A8 I7 A7 I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 I0 A0 CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 07220-038 DON'T CARE Figure 64.
AD9522-1 tS tC CS tCLK tHIGH SCLK tLOW tDS SDIO BIT N BIT N + 1 Figure 69. Serial Control Port Timing—Write Table 45.
AD9522-1 EEPROM OPERATIONS The AD9522 contains an internal EEPROM (nonvolatile memory). The EEPROM can be programmed by users to create and store a user-defined register setting file when the power is off. This setting file can be used for power-up and chip reset as a default setting. The EEPROM size is 512 bytes. During the data transfer process, the write and read registers via the serial port are generally not available except for one readback register, STATUS_EEPROM.
AD9522-1 PROGRAMMING THE EEPROM BUFFER SEGMENT IO_UPDATE (Operational Code 0x80) The EEPROM buffer segment is a register space on the AD9522 that allows the user to specify which groups of registers are stored to the EEPROM during EEPROM programming. Normally, this segment does not need to be programmed by the user. Instead, the default power-up values for the EEPROM buffer segment allow the user to store all of the AD9522 register values from Register 0x000 to Register 0x231 to the EEPROM.
AD9522-1 Table 46.
AD9522-1 THERMAL PERFORMANCE Table 47. Thermal Parameters for the 64-Lead LFCSP Symbol θJA θJMA θJMA ΨJB θJC ΨJT Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
AD9522-1 REGISTER MAP Register addresses that are not listed in Table 48 are not used, and writing to those registers has no effect. Writing to register addresses marked unused should have 0x00 written to them, unless otherwise noted. Table 48.
AD9522-1 Addr (Hex) 01E 01F Parameter PLL_CTRL_9 Bit 7 (MSB) PLL_Readback (read-only) Unused Bit 6 Unused VCO cal finished Bit 5 Holdover active Bit 4 Bit 3 External zero delay feedback channel divider select REF2 VCO freq > selected threshold Bit 2 Enable external zero delay REF2 freq > threshold Bit 1 Enable zero delay Bit 0 (LSB) Unused REF1 freq > threshold Digital lock detect N/A OUT0 LVDS power-down OUT1 LVDS power-down OUT2 LVDS power-down OUT3 LVDS power-down OUT4 LVDS power-down OU
AD9522-1 Addr (Hex) 193 194 Parameter Divider 1 Bit 7 (MSB) Divider 1 bypass 195 196 197 Divider 2 Divider 2 bypass 198 199 19A Divider 3 Divider 3 bypass 19B A02 A03 A04 Bit 3 Divider 1 start high Bit 2 Bit 1 Divider 1 high cycles Divider 1 phase offset Bit 0 (LSB) Disable Divider 1 DCC Divider 2 start high Channel 1 Reserved powerdown Divider 2 high cycles Divider 2 phase offset Disable Divider 2 DCC Divider 3 start high Channel 2 Reserved powerdown Divider 3 high cycles Divider 3 p
AD9522-1 Addr (Hex) A05 A06 A07 A08 A09 A0A A0B A0C A0D A0E A0F A10 A11 A12 A13 A14 A15 A16 A17 to AFF Parameter EEPROM Buffer Segment Register 6 EEPROM Buffer Segment Register 7 EEPROM Buffer Segment Register 8 EEPROM Buffer Segment Register 9 EEPROM Buffer Segment Register 10 EEPROM Buffer Segment Register 11 EEPROM Buffer Segment Register 12 EEPROM Buffer Segment Register 13 EEPROM Buffer Segment Register 14 EEPROM Buffer Segment Register 15 EEPROM Buffer Segment Register 16 EEPROM Buf
AD9522-1 Addr (Hex) Parameter EEPROM Control B00 EEPROM status (read-only) B01 EEPROM error checking (read-only) B02 EEPROM Control 1 B03 EEPROM Control 2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Unused Unused Unused Soft_EEPROM (self-clearing) Unused Rev.
AD9522-1 REGISTER MAP DESCRIPTIONS Table 49 through Table 59 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a specific bit or range of bits within a register is indicated by squared brackets. For example, [3] refers to Bit 3 and [5:2] refers to the range of bits from Bit 5 through Bit 2. Table 49.
AD9522-1 Table 52. PLL Reg. Addr (Hex) Bit(s) Name 010 [7] PFD polarity 010 [6:4] CP current 010 [3:2] CP mode 010 [1:0] 011 [7:0] 012 [5:0] 013 [5:0] 014 [7:0] 015 [4:0] 016 [7] 016 [6] 016 [5] 016 [4] Description Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity, [7] = 0. [7] = 0; positive (higher control voltage produces higher frequency) (default).
AD9522-1 Reg. Addr (Hex) Bit(s) Name 016 [3] B counter bypass 016 [2:0] Prescaler P 017 [7:2] STATUS pin control Description B counter bypass. This is only valid when operating the prescaler in FD mode. [3] = 0; normal (default). [3] = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. Prescaler: DM = dual modulus and FD = fixed divide. The Prescaler P is part of the feedback divider. [2] [1] [0] Mode Prescaler 0 0 0 FD Divide-by-1.
AD9522-1 Reg. Addr (Hex) Bit(s) Name 017 [1:0] 018 [7] 018 [6:5] 018 [4] 018 [3] 018 [2:1] Description [7] 1 [6] 1 [5] [4] 0 1 [3] 0 Level or Dynamic [2] Signal 0 DYN 1 1 0 1 0 1 LVL 1 1 0 1 1 0 LVL Signal at STATUS Pin Unselected reference to PLL (not available when in differential mode). Status of selected reference (status of differential reference); active low. Status of unselected reference (not available in differential mode); active low.
AD9522-1 Reg. Addr (Hex) Bit(s) Name Description 018 [0] VCO calibration Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The now sequence to initiate a calibration follows: program to 0, followed by an IO_UPDATE bit (Register 0x232[0]); then program to 1, followed by another IO_UPDATE bit (Register 0x232[0]).
AD9522-1 Reg. Addr (Hex) Bit(s) Name 01B [7] Enable VCO frequency monitor 01B [6] Enable REF2 (REFIN) frequency monitor Enable REF1 (REFIN) frequency monitor 01B [5] 01B [4:0] REFMON pin control Description Level or Dynamic [5] [4] [3] [2] [1] [0] Signal Signal at LD Pin 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode).
AD9522-1 Reg. Addr (Hex) Bit(s) Name Description [4] 0 0 1 1 1 1 01C [7] Disable switchover deglitch 01C [6] Select REF2 01C [5] Use REF_SEL pin 01C [4] Enable automatic reference switchover 01C [3] Stay on REF2 01C [2] Enable REF2 01C [1] Enable REF1 01C [0] Enable differential reference [3] 1 1 0 0 0 0 [2] 1 1 0 0 0 0 [1] 1 1 0 0 1 1 Level or Dynamic [0] Signal 0 LVL 1 LVL 0 LVL 1 DYN 0 DYN 1 DYN Signal at REFMON Pin Holdover active (active high).
AD9522-1 Reg. Addr (Hex) Bit(s) Name Description 01D [7] Enables the Status_EEPROM signal at the STATUS pin. Enable Status_EEPROM [7] = 0; the STATUS pin is controlled by the 0x017[7:2] selection. at STATUS pin [7] = 1; select the Status_EEPROM signal at STATUS pin. This bit overrides 0x017[7:2] (default). 01D [6] Enables the maintaining amplifier needed by a crystal oscillator at the PLL reference input. Enable XTAL OSC [6] = 0; crystal oscillator maintaining amplifier disabled (default).
AD9522-1 Reg. Addr (Hex) Bit(s) Name 01F [2] REF2 frequency > threshold (read-only) 01F [1] 01F [0] Description Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by Register 0x01A[6]. [2] = 0; REF2 frequency is less than the threshold frequency. [2] = 1; REF2 frequency is greater than the threshold frequency. REF1 frequency Readback register.
AD9522-1 Reg. Addr (Hex) 0F6 0F7 0F8 0F9 0FA 0FB 0FC Bit(s) [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7] Name OUT6 control OUT7 control OUT8 control OUT9 control OUT10 control OUT11 control CSDLD En OUT7 0FC 0FC 0FC 0FC 0FC 0FC 0FC 0FD [6] [5] [4] [3] [2] [1] [0] [3] 0FD [2] 0FD 0FD [1] [0] CSDLD En OUT6 CSDLD En OUT5 CSDLD En OUT4 CSDLD En OUT3 CSDLD En OUT2 CSDLD En OUT1 CSDLD En OUT0 CSDLD En OUT11 OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
AD9522-1 Reg.
AD9522-1 Reg. Addr (Hex) Bit(s) Name 198 [2] Channel 2 power-down 198 [0] Disable Divider 2 DCC 199 [7:4] Divider 3 low cycles 199 [3:0] Divider 3 high cycles 19A [7] Divider 3 bypass 19A [6] Divider 3 ignore SYNC 19A [5] Divider 3 force high 19A [4] Divider 3 start high 19A 19B [3:0] [2] Divider 3 phase offset Channel 3 power-down 19B [0] Disable Divider 3 DCC Description Channel 2 powers down. [2] = 0; normal operation (default). [2] = 1; powered down.
AD9522-1 Reg. Addr (Hex) Bit(s) Name Description 1E1 [3] Power-down VCO clock interface Powers down the interface block between VCO and clock distribution. [3] = 0; normal operation (default). [3] = 1; power down. 1E1 [2] Power-down VCO and CLK Powers down both the CLK input and VCO. [2] = 0; normal operation (default). [2] = 1; power down. 1E1 [1] Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider. [1] = 0; select external CLK as input to VCO divider (default).
AD9522-1 Table 58. EEPROM Buffer Segment Reg. Addr (Hex) Bit(s) Name A00 to [7:0] EEPROM Buffer A16 Segment Register 1 to EEPROM Buffer Segment Register 23 Description The EEPROM buffer segment section stores the starting address and number of bytes that are to be stored and read back to and from the EEPROM. Because the AD9522 register space is noncontiguous, the EEPROM controller needs to know the starting address and number of bytes in the AD9522 register space to store and retrieve from the EEPROM.
AD9522-1 APPLICATIONS INFORMATION Within the AD9522 family, lower VCO frequencies generally result in slightly lower jitter. The difference in integrated jitter (from 12 kHz to 20 MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.4 GHz to 2.95 GHz) of the AD9522 family.
AD9522-1 VS 100Ω DIFFERENTIAL (COUPLES) 100Ω LVDS 07220-047 LVDS VS The value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and signal integrity. CMOS 10Ω 60.4Ω (1.0 INCH) CMOS MICROSTRIP Figure 71.
AD9522-1 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 48 64 49 PIN 1 INDICATOR 1 PIN 1 INDICATOR 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 33 32 16 17 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 6.35 6.20 SQ 6.05 EXPOSED PAD (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 091707-C 8.
AD9522-1 NOTES Rev.
AD9522-1 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07220-0-11/08(0) Rev.