2 LVDS/24 CMOS Output Clock Generator AD9522-5 FEATURES APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.
AD9522-5 TABLE OF CONTENTS Features .............................................................................................. 1 Charge Pump (CP)................................................................. 29 Applications ....................................................................................... 1 PLL External Loop Filter ....................................................... 30 General Description .........................................................................
AD9522-5 Data Transfer Format .............................................................47 IO_UPDATE (Operational Code 0x80) .............................. 53 I2C Serial Port Timing ............................................................47 End-of-Data (Operational Code 0xFF) ............................... 53 SPI Serial Port Operation ...........................................................48 Pseudo-End-of-Data (Operational Code 0xFE) ................. 53 Pin Descriptions ..................
AD9522-5 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter VS VCP RSET Pin Resistor CPRSET Pin Resistor Min 3.135 VS Typ 3.3 Max 3.465 5.25 4.12 5.1 Unit V V kΩ kΩ Test Conditions/Comments 3.3 V ± 5% This is nominally 3.3 V to 5.
AD9522-5 Parameter CHARGE PUMP (CP) ICP Sink/Source High Value Min Low Value Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching Max Unit 4.8 mA 0.60 mA 2.5 1 1 % kΩ nA % 1.5 2 % % 2.7 ICP vs. VCP ICP vs.
AD9522-5 Parameter NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) @ 500 kHz PFD Frequency @ 1 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency PLL Figure of Merit (FOM) Min Typ Max Unit The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider) −165 −162 −152 −144 −222 dBc/Hz dBc/Hz dBc/Hz dB
AD9522-5 CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min Typ 01 01 Input Sensitivity, Differential 1 Unit 2.4 1.6 GHz GHz 150 Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Max 1.3 1.3 3.9 1.57 150 4.7 2 mV p-p 2 V p-p 1.8 1.8 V V mV p-p kΩ pF 5.
AD9522-5 TIMING CHARACTERISTICS Table 5.
AD9522-5 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter CLK-TO-LVDS ADDITIVE PHASE NOISE CLK = 1.
AD9522-5 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 7. Parameter LVDS OUTPUT ABSOLUTE TIME JITTER Min Typ LVDS = 245.76 MHz; PLL LBW = 125 Hz Max 87 108 146 120 151 207 157 210 295 LVDS = 122.88 MHz; PLL LBW = 125 Hz LVDS = 61.44 MHz; PLL LBW = 125 Hz Unit Test Conditions/Comments Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.
AD9522-5 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 9.
AD9522-5 SERIAL CONTROL PORT—I²C MODE Table 11. Parameter SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage Input Logic 0 Voltage Input Current with an Input Voltage Between 0.1 × VS and 0.
AD9522-5 PD, SYNC, AND RESET PINS Table 12. Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Min Typ Max Unit 0.8 1 −110 V V μA μA 2 pF 2.0 Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming 50 100 ns ns SYNC TIMING Pulse Width Low 1.
AD9522-5 POWER DISSIPATION Table 15. Parameter POWER DISSIPATION, CHIP Typ Max Unit Power-On Default Distribution Only Mode; VCO Divider On; One LVDS Output Enabled Distribution Only Mode; VCO Divider Off; One LVDS Output Enabled Maximum Power, Full Operation 0.88 0.36 1.0 0.43 W W 0.33 0.4 W 1.1 1.3 W PD Power-Down 35 50 mW PD Power-Down, Maximum Sleep 27 43 mW 2.
AD9522-5 ABSOLUTE MAXIMUM RATINGS Table 16. Parameter or Pin VS VCP, CP REFIN, REFIN RSET CPRSET CLK, CLK CLK SCLK/SCL, SDIO/SDA, SDO, CS OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, OUT9, OUT9, OUT10, OUT10, OUT11, OUT11 SYNC, RESET, PD REFMON, STATUS, LD SP0, SP1, EEPROM Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec) 1 With Respect to GND GND GND GND GND GND CLK GND GND Rating −0.3 V to +3.6 V −0.3 V to +5.8 V −0.
AD9522-5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 REFIN (REF1) REFIN (REF2) CPRSET VS VS GND RSET VS OUT0 (OUT0A) OUT0 (OUT0B) VS OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) VS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9522-5 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OUT3 (OUT3A) OUT3 (OUT3B) VS OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) VS VS OUT8 (OUT8B) OUT8 (OUT8A) OUT7 (OUT7B) OUT7 (
AD9522-5 Pin No. 15 Input/ Output I Pin Type 3.3 V CMOS Mnemonic CS 16 I 3.3 V CMOS SCLK/SCL 17 18 19, 59 20 I/O O I I SDIO/SDA SDO GND SP1 21 I 22 I 3.3 V CMOS 3.3 V CMOS GND Three-level logic Three-level logic 3.3 V CMOS 23 24 25 I I O RESET PD OUT9 (OUT9A) 26 O 28 O 29 O 30 O 31 O 33 O 34 O 36 O 37 O 38 O 39 O 42 O 43 O 44 O 45 O 3.3 V CMOS 3.
AD9522-5 Pin No. 47 Input/ Output O 48 O 50 O 51 O 52 O 53 O 55 O 56 O 58 O 62 O 63 I 64 I EPAD Pin Type LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS Current set resistor Current set resistor Reference input Reference input GND Mnemonic OUT3 (OUT3B) OUT3 (OUT3A) OUT2 (OUT2B) OUT2 (OUT2A) OUT1 (OUT1B) OUT1 (OUT1A) OUT0 (OUT0B) OUT0 (OUT0A) RSET CPRSET REFIN (REF2) REFIN (REF1) GND Description Clock Output.
AD9522-5 TYPICAL PERFORMANCE CHARACTERISTICS 275 5 3 CHANNELS—6 LVDS 250 3 CHANNELS—3 LVDS 200 175 2 CHANNELS—2 LVDS 150 4 CURRENT FROM CP PIN (mA) 125 PUMP DOWN 3 2 1 1 CHANNEL—1 LVDS 0 200 400 600 800 1000 FREQUENCY (MHz) 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 07240-112 75 07240-108 100 5.0 VOLTAGE ON CP PIN (V) Figure 6. Total Current vs.
AD9522-5 3.5 3.2 VS_DRV = 3.3V 3.0 2.8 VS_DRV = 3.135V AMPLITUDE (V) VS_DRV = 2.35V 2.0 1.5 1.0 2.0 1.6 1.2 0.8 0.5 0 1k 100 RESISTIVE LOAD (Ω) 0 07240-118 0 10k 10 20 30 40 0.4 70 80 90 100 2pF LOAD 3.2 0.3 2.8 10pF LOAD AMPLITUDE (V) 2.4 0.1 0 –0.1 2.0 1.6 1.2 –0.2 0.8 –0.3 0.4 –0.4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TIME (ns) 0 0 1 2 3 4 5 6 7 8 10 9 TIME (ns) Figure 13.
AD9522-5 4.0 –100 3.5 –110 PHASE NOISE (dBc/Hz) 3.0 AMPLITUDE (V) 2pF 2.5 2.0 10pF 1.5 20pF 1.0 –120 –130 –140 100 200 300 400 500 600 700 FREQUENCY (MHz) –150 10 –110 –120 PHASE NOISE (dBc/Hz) 100k 1M 10M 100M –120 –130 –140 –130 –140 –150 –160 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) –170 10 07240-128 100 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 07240-131 PHASE NOISE (dBc/Hz) –110 –150 Figure 22.
AD9522-5 –80 INTEGRATED RMS JITTER (12kHz TO 20MHz): 146fs PHASE NOISE (dBc/Hz) –90 –100 –110 –120 –130 –140 –160 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 07240-135 –150 Figure 24. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVDS Output = 245.76 MHz Rev.
AD9522-5 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave has a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, have a variation from the ideal phase progression over time. This variation is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as a Gaussian (normal) distribution.
AD9522-5 DETAILED BLOCK DIAGRAM VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0 DIGITAL LOGIC EEPRO
AD9522-5 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9522 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 43 to Table 54). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers.
AD9522-5 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0 DIGITAL LOGIC EEPROM RESET OUT1 OUT1 OU
AD9522-5 Mode 2: High Frequency Clock Distribution—CLK or External VCO > 1600 MHz When using the PLL with an external VCO, the PLL must be turned on. The AD9522 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6).
AD9522-5 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD REFIN AMP STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK OUT0 CLK OUT0 1 DIVIDE BY 1 TO 32 PD SYNC 0 DIGITAL LOGIC EEPROM RESET OUT1 OUT1 OU
AD9522-5 Phase-Locked Loop (PLL) VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF REFIN LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD STATUS AMP P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK FROM CHANNEL DIVIDER 0 1 07240-064 CLK 0 Figure 28.
AD9522-5 PLL External Loop Filter An example of an external loop filter for a PLL is shown in Figure 29. A loop filter must be calculated for each desired PLL configuration. The values of the components depend on the VCO frequency, the KVCO, the PFD frequency, the charge pump current, the desired loop bandwidth, and the desired phase margin. The loop filter affects the phase noise, the loop settling time, and the loop stability.
AD9522-5 There are several configurable modes of reference switchover. The switchover can be performed manually or automatically. Manual switchover is performed either through Register 0x01C or by using the REF_SEL pin. The automatic switchover occurs when REF1 disappears. A switchover deglitch feature ensures that the PLL does not receive rising edges that are far out of alignment with the newly selected reference. operation are given in Table 47, 0x016[2:0].
AD9522-5 Table 25.
AD9522-5 The current source lock detect provides a current of 110 μA when DLD is true and shorts to ground when DLD is false. If a capacitor is connected to the LD pin, it charges at a rate determined by the current source during the DLD true time but is discharged nearly instantly when DLD is false. By monitoring the voltage at the LD pin (top of the capacitor), LD = high happens only after the DLD is true for a sufficiently long time. Any momentary DLD false resets the charging.
AD9522-5 PLL ENABLED LOOP OUT OF LOCK. DIGITAL LOCK DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK AS DETERMINED BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD. NO DLD == LOW YES NO ANALOG LOCK DETECT PIN INDICATES LOCK WAS PREVIOUSLY ACHIEVED. (0x01D[3] = 1; USE LD PIN VOLTAGE WITH HOLDOVER. 0x01D[3] = 0; IGNORE LD PIN VOLTAGE, TREAT LD PIN AS ALWAYS HIGH.) WAS LD PIN == HIGH WHEN DLD WENT LOW? YES CHARGE PUMP IS MADE HIGH IMPEDANCE. PLL COUNTERS CONTINUE OPERATING NORMALLY.
AD9522-5 When in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present. As in the external holdover mode, the B counter (in the N divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path PFD event. This helps align the edges out of the R and N dividers for faster settling of the PLL and reduces frequency errors during settling.
AD9522-5 VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD STATUS BUF REFIN LOCK DETECT PLL REFERENCE STATUS REF2 R DIVIDER CLOCK DOUBLER REF1 OPTIONAL REFIN CPRSET VCP PROGRAMMABLE R DELAY REF_SEL HOLD CLK FREQUENCY STATUS P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP N DIVIDER ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK 1 07240-070 FROM CHANNEL DIVIDER 0 CLK 0 Figure 35.
AD9522-5 EXTERNAL VCXO REFIN/ REFIN R DIVIDER AD9522-5 R DELAY PFD N DIVIDER LOOP FILTER CP N DELAY REG 0x01E[1] = 1 MUX1 INTERNAL ZERO DELAY CLOCK FEEDBACK PATH DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK/CLK CHANNEL DIVIDER 0 OUT0 TO OUT2 CHANNEL DIVIDER 1 OUT3 TO OUT5 CHANNEL DIVIDER 2 OUT6 TO OUT8 CHANNEL DIVIDER 3 OUT9 TO OUT11 0 07240-053 1 Figure 36.
AD9522-5 PLL DIVIDE BY 1, 2, 3, 4, 5, OR 6 DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK CLK 1 0 DISTRIBUTION CLOCK 1 CLOCK DISTRIBUTION MODE 1 (CLOCK DISTRIBUTION MODE) 0 DISTRIBUTION CLOCK CLOCK DISTRIBUTION MODE 2 (HF CLOCK DISTRIBUTION MODE) 07240-054 CLK PLL Figure 37. Simplified Diagram of the Two Clock Distribution Operation Modes CLOCK DISTRIBUTION Operation Modes A clock channel consists of three LVDS clock outputs or six CMOS clock outputs that share a common divider.
AD9522-5 The channel dividers feeding the output drivers contain one 2-to-32 frequency divider. This divider provides for division-by-1 to division-by-32. Division-by-1 is accomplished by bypassing the divider. The dividers also provide for a programmable duty cycle, with optional duty-cycle correction when the divide ratio is odd. A phase offset or delay in increments of the input clock cycle is selectable. The channel dividers operate with a signal at their inputs up to 1600 MHz.
AD9522-5 If the CLK input is routed directly to the output, the duty cycle of the output is the same as the CLK input. Table 30. Channel Divider Output Duty Cycle with VCO Divider ≠ 1, Input Duty Cycle Is X% DX VCO Divider Even Even N+M+2 Channel divider bypassed Channel divider bypassed Channel divider bypassed Even Even Odd Odd = 3 Even Odd = 3 Odd Odd = 5 Even Odd = 5 Odd Odd = 3 Odd = 5 Output Duty Cycle Disable Div DCC = 1 Disable Div DCC = 0 50% 50% 33.
AD9522-5 By giving each divider a different phase offset, output-to-output delays can be set in increments of the channel divider input clock cycle. Figure 38 shows the results of setting such a coarse offset between outputs. CHANNEL DIVIDER INPUT 0 1 2 Tx 3 4 5 6 7 8 9 10 11 12 13 14 15 CHANNEL DIVIDER OUTPUTS DIV = 4, DUTY = 50% DIVIDER 1 SH = 0 PO = 1 DIVIDER 2 SH = 0 PO = 2 07240-071 SH = 0 DIVIDER 0 PO = 0 1 × Tx 2 × Tx Figure 38.
AD9522-5 CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC INPUT TO VCO DIVIDER 1 1 INPUT TO CHANNEL DIVIDER 2 3 4 5 6 7 9 8 11 10 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 07240-073 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT Figure 39.
AD9522-5 CMOS Output Drivers Soft Reset via the Serial Port The user can also individually configure each LVDS output as a pair of CMOS outputs, which provides up to 24 CMOS outputs. When an output is configured as CMOS, CMOS Output A and CMOS Output B are automatically turned on. For a given differential pair, either CMOS Output A or Output B can be turned on or off independently.
AD9522-5 PLL Power-Down Individual Clock Output Power-Down The PLL section of the AD9522 can be selectively powered down. There are two PLL power-down modes set by Register 0x010[1:0]: asynchronous and synchronous. Any of the clock distribution outputs can be put into powerdown mode by individually writing to the appropriate registers. The register map details the individual power-down settings for each output. These settings are found in Register 0x0F0[0] to Register 0x0FB[0].
AD9522-5 SERIAL CONTROL PORT The AD9522 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9522 serial control port is compatible with most synchronous transfer formats, including Philips I2C, Motorola® SPI®, and Intel® SSR protocols.
AD9522-5 MSB ACKNOWLEDGE FROM SLAVE-RECEIVER 1 SCL 2 3 TO 7 8 9 1 ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 8 9 S 10 P 07240-162 SDA Figure 45. Acknowledge Bit MSB = 0 1 SCL 2 3 TO 7 8 9 1 ACKNOWLEDGE FROM SLAVE-RECEIVER 2 3 TO 7 8 9 S 10 P 07240-163 ACKNOWLEDGE FROM SLAVE-RECEIVER 10 P 07240-164 SDA Figure 46.
AD9522-5 Data Transfer Format Send byte format—the send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A RAM Address High Byte A RAM Address Low Byte A P Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
AD9522-5 SPI SERIAL PORT OPERATION Pin Descriptions SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 30 kΩ resistor to ground.
AD9522-5 The default mode of the AD9522 serial control port is the bidirectional mode. In bidirectional mode, both the sent data and the readback data appear on the SDIO pin. It is also possible to set the AD9522 to unidirectional mode (0x000[7] = 1 and 0x000[0] = 1). In unidirectional mode, the readback data appears on the SDO pin. A readback request reads the data that is in the serial control port buffer area or the data that is in the active registers (see Figure 50).
AD9522-5 Table 39. Serial Control Port, 16-Bit Instruction Word, MSB First MSB LSB I15 R/W I14 W1 I13 W0 I12 A12 = 0 I11 A11 = 0 I10 A10 = 0 I9 A9 I8 A8 I7 A7 I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 I0 A0 CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 07240-038 DON'T CARE Figure 51.
AD9522-5 tS tC CS tCLK tHIGH SCLK tLOW tDS SDIO BIT N BIT N + 1 Figure 56. Serial Control Port Timing—Write Table 40.
AD9522-5 EEPROM OPERATIONS The AD9522 contains an internal EEPROM (nonvolatile memory). The EEPROM can be programmed by users to create and store a user-defined register setting file when the power is off. This setting file can be used for power-up and chip reset as a default setting. The EEPROM size is 512 bytes. During the data transfer process, the write and read registers via the serial port are generally not available except for one readback register, STATUS_EEPROM.
AD9522-5 End-of-Data (Operational Code 0xFF) There are three operational codes: IO_UPDATE, end-of-data, and pseudo-end-of-data. It is important that the EEPROM buffer segment always have either an end-of-data or a pseudo-end-of-data operational code and that an IO_UPDATE operation code appear at least once before the end-of-data op code. The EEPROM controller uses Operational Code 0xFF to terminate the data transfer process between EEPROM and the control register during the upload and download process.
AD9522-5 THERMAL PERFORMANCE Table 42. Thermal Parameters for the 64-Lead LFCSP Symbol θJA θJMA θJMA ΨJB θJC ΨJT Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
AD9522-5 REGISTER MAP Register addresses that are not listed in Table 43 are not used, and writing to those registers has no effect. The user should avoid writing values other than 0x00 to register addresses marked unused. Table 43.
AD9522-5 Addr (Hex) 01E 01F Parameter PLL_CTRL_9 Bit 7 (MSB) PLL_Readback (read-only) Bit 6 Bit 5 Unused Bit 4 Unused Holdover active REF2 selected Bit 3 Bit 2 CLK freq > threshold REF2 freq > threshold Bit 1 Enable zero delay REF1 freq > threshold Output Driver Control 0F0 OUT0 control OUT0 format OUT0 CMOS configuration OUT0 polarity OUT0 LVDS differential voltage 0F1 OUT1 control OUT1 format OUT1 CMOS configuration OUT1 polarity OUT1 LVDS differential voltage 0F2 OUT2 control
AD9522-5 Addr (Hex) 193 194 Parameter Divider 1 Bit 7 (MSB) Divider 1 bypass 195 196 197 Divider 2 Divider 2 bypass 198 199 19A Divider 3 Divider 3 bypass 19B Bit 6 Bit 5 Divider 1 low cycles Divider 1 Divider 1 force ignore SYNC high Unused Divider 2 low cycles Divider 2 Divider 2 ignore force SYNC high Unused Divider 3 low cycles Divider 3 Divider 3 force ignore high SYNC Unused Unused 1E2 to 22A System 230 Power-down and SYNC A02 A03 A04 EEPROM Buffer Segment Register 2 EEPROM Buffer Se
AD9522-5 Addr (Hex) A05 A06 A07 A08 A09 A0A A0B A0C A0D A0E A0F A10 A11 A12 A13 A14 A15 A16 A17 to AFF Parameter EEPROM Buffer Segment Register 6 EEPROM Buffer Segment Register 7 EEPROM Buffer Segment Register 8 EEPROM Buffer Segment Register 9 EEPROM Buffer Segment Register 10 EEPROM Buffer Segment Register 11 EEPROM Buffer Segment Register 12 EEPROM Buffer Segment Register 13 EEPROM Buffer Segment Register 14 EEPROM Buffer Segment Register 15 EEPROM Buffer Segment Register 16 EEPROM Buf
AD9522-5 Addr (Hex) Parameter EEPROM Control B00 EEPROM status (read-only) B01 EEPROM error checking (read-only) B02 EEPROM Control 1 B03 EEPROM Control 2 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Unused Unused Unused Soft_EEPROM (self-clearing) Unused Rev.
AD9522-5 REGISTER MAP DESCRIPTIONS Table 44 through Table 54 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a specific bit or range of bits within a register is indicated by squared brackets. For example, [3] refers to Bit 3 and [5:2] refers to the range of bits from Bit 5 through Bit 2. Table 44.
AD9522-5 Table 47. PLL Reg. Addr (Hex) Bit(s) Name 010 [7] PFD polarity 010 [6:4] 010 [3:2] 010 [1:0] 011 [7:0] 012 [5:0] 013 [5:0] 014 [7:0] 015 [4:0] 016 [7] 016 [6] 016 [5] 016 [4] Description Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. [7] = 0; positive (higher control voltage produces higher frequency) (default). [7] = 1; negative (higher control voltage produces lower frequency). CP current Charge pump current (with CPRSET = 5.
AD9522-5 Reg. Addr (Hex) Bit(s) Name 016 [3] B counter bypass 016 [2:0] Prescaler P 017 [7:2] STATUS pin control Description B counter bypass. This is valid only when operating the prescaler in FD mode. [3] = 0; normal (default). [3] = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. Prescaler: DM = dual modulus and FD = fixed divide. The Prescaler P is part of the feedback divider. [2] [1] [0] Mode Prescaler 0 0 0 FD Divide-by-1.
AD9522-5 Reg.
AD9522-5 Reg. Addr (Hex) Bit(s) Name 01A [7] Enable STATUS pin divider 01A [6] 01A [5:0] Description Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the R and N dividers. [7] = 0; divide-by-4 disabled on STATUS pin (default). [7] = 1; divide-by-4 enabled on STATUS pin. Ref freq monitor Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency.
AD9522-5 Reg. Addr (Hex) Bit(s) Name 01B [7] Enable CLK frequency monitor 01B [6] Enable REF2 (REFIN) frequency monitor Enable REF1 (REFIN) frequency monitor 01B [5] 01B [4:0] REFMON pin control Description Level or Dynamic [5] [4] [3] [2] [1] [0] Signal Signal at LD Pin 1 1 1 0 1 0 LVL (DLD) AND (Status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of CLK frequency (active low). 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL DLD; active low.
AD9522-5 Reg. Addr (Hex) Bit(s) Name Description [4] 1 01C [7] 01C [6] 01C [5] 01C [4] 01C [3] 01C [2] 01C [1] 01C [0] 01D [7] 01D [6] [3] 0 [2] 1 [1] 0 Level or Dynamic [0] Signal 1 LVL Signal at REFMON Pin Status of selected reference (status of differential reference); active low. 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 0 0 0 LVL Status of REF2 frequency (active low).
AD9522-5 Reg. Addr (Hex) Bit(s) Name 01D [5] Enable clock doubler 01D [4] 01D [3] 01D [1] 01D [0] 01E [1] 01F [5] 01F [4] 01F [3] 01F [2] 01F [1] 01F [0] Description Enable PLL reference input clock doubler. [5] = 0; doubler disabled (default). [5] = 1; doubler enabled. Disables the PLL status register readback. Disable PLL status register [4] = 0; PLL status register enabled (default). [4] = 1; PLL status register disabled. If this bit is set, 0x01F is not automatically updated.
AD9522-5 Table 48. Output Driver Control Reg.
AD9522-5 Reg. Addr (Hex) 0FC 0FC 0FC 0FD Bit(s) [2] [1] [0] [3] 0FD [2] 0FD 0FD [1] [0] Name CSDLD En OUT2 CSDLD En OUT1 CSDLD En OUT0 CSDLD En OUT11 CSDLD En OUT10 CSDLD En OUT9 CSDLD En OUT8 Description OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT11 is enabled only if CSDLD is high.
AD9522-5 Reg.
AD9522-5 Reg. Addr (Hex) Bit(s) Name 19B [2] Channel 3 power-down 19B [0] Disable Divider 3 DCC Description Channel 3 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are put into the high impedance power-down mode by setting this bit.) Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. Table 50. VCO Divider and CLK Input Reg.
AD9522-5 Table 52. Update All Registers Reg. Addr (Hex) Bit(s) Name 232 [0] IO_UPDATE Description This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not need to be set back to 0. [0] = 1 (self-clearing); update all active registers to the contents of the buffer registers. Table 53. EEPROM Buffer Segment Reg.
AD9522-5 APPLICATIONS INFORMATION 110 FREQUENCY PLANNING USING THE AD9522 The AD9522 is a highly flexible PLL. When choosing the PLL settings and version of the AD9522, the following guidelines should be kept in mind. ADIsimCLK is a powerful PLL modeling tool that can be downloaded from www.analog.com. ADIsimCLK is a very accurate tool for determining the optimal loop filter for a given application.
AD9522-5 CMOS CLOCK DISTRIBUTION The output drivers of the AD9522 can be configured as CMOS drivers. When selected as a CMOS driver, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as inverting or noninverting. These outputs are 3.3 V CMOS compatible. When single-ended CMOS clocking is used, some of the following guidelines apply. VS The value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used).
AD9522-5 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 48 64 49 PIN 1 INDICATOR 1 PIN 1 INDICATOR 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 33 32 16 17 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 6.35 6.20 SQ 6.05 EXPOSED PAD (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 091707-C 8.
AD9522-5 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07240-0-12/08(0) Rev.