Datasheet

AD9522-1
Rev. 0 | Page 44 of 84
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (1, 2, 3, 4, 5, or 6) and
the division of the channel divider. Table 32 indicates how the
frequency division for a channel is set.
Table 32. Frequency Division
CLK or VCO
Selected
VCO Divider
Setting
1
Channel
Divider
Setting
Resulting
Frequency
Division
CLK or VCO input 1 to 6 2 to 32
(1 to 6) × (2 to
32)
CLK or VCO input 2 to 6 Bypass (2 to 6) × (1)
CLK or VCO input 1 Bypass
Output static
(illegal state)
CLK (internal
VCO off)
VCO divider
bypassed
Bypass 1
CLK (internal
VCO off)
VCO divider
bypassed
2 to 32 2 to 32
1
The bypass VCO divider (0x1E1[0] = 1) is not the same as VCO divider = 1.
The channel dividers feeding the output drivers contain one
2-to-32 frequency divider. This divider provides for division-by-1
to division-by-32. Division-by-1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 48 through Table 59).
VCO Divider
The VCO divider provides frequency division between the
internal VCO or the external CLK input and the clock distribution
channel dividers. The VCO divider can be set to divide by 1, 2,
3, 4, 5, or 6 (see Table 55, 0x1E0[2:0]). However, when the VCO
divider is set to 1, none of the channel output dividers can be
bypassed.
The VCO divider can also be set to static, which is useful for
applications where the only desired output frequency is the
VCO frequency. Making the VCO divider static increases the
wideband spurious-free dynamic range (SFDR). If the VCO
divider is static during VCO calibration, there is no output
signal. Therefore, it is recommended that the user calibrate the
VCO with the VCO divider set to a nonstatic value during VCO
calibration, and then set the VCO divider to static after VCO
calibration is complete.
The same improvement in SFDR performance can also be
achieved by setting the VCO divider to 1. This allows the user
to program the EEPROM with the desired values and does not
require further action after the VCO calibration is complete.
Channel Dividers
A channel divider drives each group of three LVDS outputs.
There are four channel dividers (0, 1, 2, and 3) driving 12 LVDS
outputs (OUT0 to OUT11). Table 33 gives the register locations
used for setting the division and other functions of these dividers.
The division is set by the values of M and N. The divider can be
bypassed (equivalent to divide-by-1, divider circuit is powered
down) by setting the bypass bit. The duty-cycle correction can
be enabled or disabled according to the setting of the disable
divider DCC bits.
Table 33. Setting D
X
for the Output Dividers
Divider Low Cycles M High Cycles N Bypass
Disable
Div DCC
0 0x190[7:4] 0x190[3:0] 0x191[7] 0x192[0]
1 0x193[7:4] 0x193[3:0] 0x194[7] 0x195[0]
2 0x196[7:4] 0x196[3:0] 0x197[7] 0x198[0]
3 0x199[7:4] 0x199[3:0] 0x19A[7] 0x19B[0]
Channel Frequency Division (0, 1, 2, and 3)
For each channel (where the channel number x is 0, 1, 2, or 3),
the frequency division, D
X
, is set by the values of M and N
(four bits each, representing Decimal 0 to Decimal 15), where
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
The high and low cycles are cycles of the clock signal currently routed
to the input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, D
X
= 1.
Otherwise, D
X
= (N + 1) + (M + 1) = N + M + 2. This allows
each channel divider to divide by any integer from 1 to 32.
Duty Cycle and Duty-Cycle Correction
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
• The M and N values for the channel
• DCC enabled/disabled
• VCO divider enabled/bypassed
• The CLK input duty cycle (note that the internal VCO has
a 50% duty cycle)
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the disable divider DCC bit for
that channel.
Certain M and N values for a channel divider result in a non-
50% duty cycle. A non-50% duty cycle can also result with an
even division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle.