Datasheet

Data Sheet AD9524
Rev. D | Page 47 of 56
Output PLL (PLL2) (Address 0x0F0 to Address 0x0F9)
Table 45. PLL2 Charge Pump Control
Table 46. PLL2 Feedback N Divider Control
Table 47. PLL2 Control
Address Bits Bit Name Description
0x0F2 7 PLL2 lock detector power-down Controls power-down of the PLL2 lock detector.
1: lock detector powered down.
0: lock detector active.
6 Reserved Default = 0; value must remain 0.
5 Enable frequency doubler Enables doubling of the PLL2 reference input frequency.
1: enabled.
0: disabled.
4 Enable SPI control of antibacklash
pulse width
Controls the functionality of Register 0x0F2, Bits[3:2]. Set the antibacklash pulse
width to the minimum setting. By setting Bit 4 to 1 from the default of 0, Bits[3:2]
consequently default to 00.
0 (default): device automatically controls the antibacklash period to high
(equivalent to Register 0x0F2, Bits[3:2] = 10).
1: antibacklash period defined by Register 0x0F2, Bits[2:1] (recommended setting).
[3:2] Antibacklash pulse width control Controls the PFD antibacklash period of PLL2.
00 (default): minimum (recommended setting).
01: low.
10: high.
11: maximum.
These bits are ineffective unless Register 0x0F2, Bit 4 = 1.
[1:0] PLL2 charge pump mode Controls the mode of the PLL2 charge pump.
00: tristate.
01: pump up.
10: pump down.
11 (default): normal.
Address Bits Bit Name Description
0x0F0 [7:0] PLL2 charge pump control These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 μA
with a full-scale magnitude of ~900 μA.
Address Bits Bit Name Description
0x0F1 [7:6] A counter A counter word
[5:0] B counter B counter word
Feedback Divider Constraints
A Counter (Bits[7:6])
B Counter (Bits[5:0])
Allowed N Division (4 × B + A)
A = 0 or A = 1
B = 4
16, 17
A = 0 to A = 2 B = 5 20, 21, 22
A = 0 to A = 2 B = 6 24, 25, 26
A = 0 to A = 3
B ≥ 7 28, 29 … continuous to 255