Datasheet

Data Sheet AD9524
Rev. D | Page 51 of 56
Address Bits Bit Name Description
0x198 [7:2] Divider phase Divider initial phase after a sync is asserted relative to the divider input clock (from the
VCO divider output). LSB = ½ of a period of the divider input clock.
Phase = 0: no phase offset.
Phase = 1: ½ period offset, …
Phase = 63: 31 period offset.
[1:0] Channel divider, Bits[9:8] (MSB) 10-bit channel divider, Bits[9:8] (MSB).
Table 52. PLL1 Output Control (PLL1_OUT, Pin 46)
Address Bits Bit Name Description
0x1BA [7:5] Reserved Reserved
4 PLL1 output CMOS driver
strength
CMOS driver strength
1: weak
0: strong
[3:0] PLL1 output divider 0000: divide-by-1
0001: divide-by-2 (default)
0010: divide-by-4
0100: divide-by-8
1000: divide-by-16
No other inputs permitted
Table 53. PLL1 Output Channel Control
Address Bits Bit Name Description
0x1BB 7 PLL1 output driver power-down PLL1 output driver power-down
[6:2] Reserved Reserved
1 Route VCXO clock to
Channel 1 divider input
1: channel uses VCXO clock. Routes VCXO clock to divider input
0: channel uses VCO divider output clock
0 Route VCXO clock to
Channel 0 divider input
1: channel uses VCXO clock. Routes VCXO clock to divider input
0: channel uses VCO divider output clock
Readback (Address 0x22C to Address 0x22D)
Table 54. Readback Registers (Readback 0 and Readback 1)
Address Bits Bit Name Description
0x22C 7 Status PLL2 reference clock 1: OK
0: off/clocks are missing
6 Status PLL1 feedback clock 1: OK
0: off/clocks are missing
5 Status VCXO 1: OK
0: off/clocks are missing
4 Status REF_TEST 1: OK
0: off/clocks are missing
3 Status REFB 1: OK
0: off/clocks are missing
2 Status REFA 1: OK
0: off/clocks are missing
1 Lock detect PLL2 1: locked
0: unlocked
0 Lock detect PLL1 1: locked
0: unlocked