Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9525BCPZ

Low Jitter Clock Generator

with Eight LVPECL Outputs

Data Sheet

AD9525

Rev. A Document Feedback

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FEATURES

Integrated ultralow noise synthesizer

8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC

output or 2 CMOS SYNC outputs

2 differential reference inputs and 1 single-ended reference

input

APPLICATIONS

LTE and multicarrier GSM base stations

Clocking high speed ADCs, DACs

ATE and high performance instrumentation

40/100 Gb/sec OTN line side clocking

Cable/DOCSIS CMTS clocking

Test and measurement

FUNCTIONAL BLOCK DIAGRAM

REFB

PLL

DIVIDERS

÷S

SPI CONTROL

AD9525

REFA

REFB

SYNC_OUT

REFC

CLKIN

OUT7

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

OUT0

10011-001

Figure 1.

GENERAL DESCRIPTION

The AD9525 is designed to support converter clock requirements

for long-term evolution (LTE) and multicarrier GSM base station

designs.

The AD9525 provides a low power, multioutput, clock distribution

function with low jitter performance, along with an on-chip PLL

that can be used with an external VCO or VCXO. The VCO input

and eight LVPECL outputs can operate up to a frequency of

3.6 GHz. All outputs share a common divider that can provide

a division of 1 to 6.

The AD9525 offers a dedicated output that can be used to provide

a programmable signal for resetting or synchronizing a data

converter. The output signal is activated by a SPI write.

The AD9525 is available in a 48-lead LFCSP and can be operated

from a single 3.3 V supply. The external VCXO or VCO can

have an operating voltage of up to 5.5 V.

The AD9525 operates over the extended industrial temperature

range of −40°C to +85°C.

Summary of content (48 pages)

PAGE 1
Low Jitter Clock Generator with Eight LVPECL Outputs AD9525 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Integrated ultralow noise synthesizer 8 differential 3.
PAGE 2
AD9525 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ......................................................... 12 Applications ....................................................................................... 1 Thermal Resistance .................................................................... 12 Functional Block Diagram ...........................................................
PAGE 3
Data Sheet AD9525 SPECIFICATIONS Typical is given for VDD3 = 3.3 V ± 5%; VDD3 ≤ VDD_CP ≤ 5.25 V; TA = 25°C; OUT_RSET resistor = 4.12 kΩ; CP_RSET resistor (CPRSET) = 5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VDD3 and TA (−40°C to +85°C) variation as listed in Table 1. REFA at 122.88 MHz, CLKIN frequency = 2949.12 MHz. CONDITIONS Table 1.
PAGE 4
AD9525 Parameter POWER DELTAS, INDIVIDUAL FUNCTIONS M Divider On/Off P Divider On/Off B Divider On/Off REFB On PLL On/Off Data Sheet Min Typ Max Unit 5 3 16 15 254 8.7 5.7 23.1 25 300.5 mW mW mW mW mW One Channel, One Driver 107 132 mW One Channel, Two Drivers 184 233 mW Typ Max Unit 500 MHz 1.78 1.61 4.9 5.
PAGE 5
Data Sheet AD9525 CLOCK INPUTS Table 6. Parameter Input Frequency Min 0 Typ Input Sensitivity Input Level 150 Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Resistance Input Capacitance 1.55 1.3 6.7 1.64 Min Typ 7 2 Max 3.6 Unit GHz 2 mV p-p V p-p Test Conditions/Comments Frequencies below ~1 MHz should be dc-coupled; be careful to match self-bias voltage Measured at 3.
PAGE 6
AD9525 Data Sheet PLL DIGITAL LOCK DETECT Table 8. Parameter PLL DIGITAL LOCK DETECT WINDOW 1 Min Typ Max Unit Lock Threshold (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6.0 ns) Unlock Threshold (Hysteresis)1 Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6.0 ns) 1 4 7 3.5 ns ns ns 8.3 16.
PAGE 7
Data Sheet AD9525 TIMING CHARACTERISTICS Table 10.
PAGE 8
AD9525 Data Sheet CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 122.88 MHZ VCXO) Table 11. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min FOUT = 122.88 MHz Typ Max 107 69 108 107 FOUT = 61.44 MHz Unit fs rms fs rms fs rms fs rms Test Conditions/Comments Application example based on a typical setup using an external 122.88 MHz VCXO (Crystek CVHD-950); reference = 122.
PAGE 9
Data Sheet AD9525 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 2.05 GHZ VCO) Table 14. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min FOUT = 2048.867 MHz Typ Max 19 21 87 −105 Reference Sideband Spurs Unit fs rms fs rms fs rms dBc Test Conditions/Comments Application example based on a typical setup using an external 2.05 MHz VCO (Bowei Model MVCO2050A); reference = 122.
PAGE 10
AD9525 Parameter CLK = 1474.56 MHz, FOUT = 1474.56 MHz Divider = 1 At 10 Hz Offset At 100 Hz Offset At 1 kHz Offset At 10 kHz Offset At 100 kHz Offset At 800 kHz Offset At 1 MHz Offset At 10 MHz Offset CLK = 122.88 MHz, FOUT = 122.
PAGE 11
Data Sheet AD9525 SERIAL CONTROL PORT Table 19.
PAGE 12
AD9525 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 20. Parameter VDD3 to GND VDD_CP, CP to GND REFA, REFA, REFB, REFB, REFC to GND OUT_RSET to GND CP_RSET to GND CLKIN, CLKIN to GND CLKIN to CLKIN SCLK, SDIO, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, SYNC_OUT, SYNC_OUT to GND RESET, PD, STATUS, REF_MON to GND Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec) 1 Rating −0.3 V to +3.6 V −0.3 V to +5.8 V −0.
PAGE 13
Data Sheet AD9525 48 47 46 45 44 43 42 41 40 39 38 37 OUT2 OUT2 VDD3 OUT3 OUT3 OUT4 OUT4 VDD3 OUT5 OUT5 OUT6 OUT6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9525 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 VDD3 OUT7 OUT7 REF_MON VDD3 SYNC_OUT SYNC_OUT GND SDO SDIO SCLK CS NOTES 1. THE EXPOSED PAD IS A GROUND CONNECTION ON THE CHIP THAT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
PAGE 14
AD9525 Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 EP Mnemonic SDO GND SYNC_OUT SYNC_OUT VDD3 REF_MON OUT7 OUT7 VDD3 OUT6 OUT6 OUT5 OUT5 VDD3 OUT4 OUT4 OUT3 OUT3 VDD3 OUT2 OUT2 EP, GND Data Sheet Type I GND O O P O O O P O O O O P O O O O P O O GND Description Serial Control Port Unidirectional Serial Data Out. Connect to ground. LVPECL Complementary Output for Programmable Sync Signal. LVPECL Output for Programmable Sync Signal. Power Supply for SYNC_OUT Driver.
PAGE 15
Data Sheet AD9525 TYPICAL PERFORMANCE CHARACTERISTICS 6 CURRENT FROM CP PIN (mA) 5 PUMP UP PUMP DOWN 4 1 3 2 0 1 2 VOLTAGE ON CP PIN (V) 3 4 CH1 500mV Ω Figure 5. Charge Pump Characteristics at VDD_CP = 3.3 V 2.5 PUMP UP PUMP DOWN 4 3 2 1 0 1 2 3 4 5 6 VOLTAGE ON CP PIN (V) –218.5 –219.0 –219.5 –220.0 –220.5 –221.0 –221.5 –222.5 0.6 0.8 1.0 1.2 10011-007 –222.0 0.4 600mV p-p 1.5 1.3 400mV p-p 1.1 0.9 0.7 500 1000 1500 2000 2500 3000 Figure 9.
PAGE 16
AD9525 Data Sheet –80 –20 –90 –40 1: 2: 3: 4: 5: 6: 7: –30 –50 –60 –130 –140 –90 –100 –130 –150 –160 –160 –170 20M 10011-010 10M 1M 100k 10k 1k 100 10 –20 –90 –30 –40 –100 –50 –60 –110 –70 –80 –130 –140 –150 –160 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 11. Additive (Residual) Phase Noise, CLK-to-LVPECL at 1500 MHz, Divide-by-1 –110 –120 –50 1kHz, –103.4dBc/Hz 10kHz, –109.2dBc/Hz 100kHz, –130.6dBc/Hz 800kHz, –147.3dBc/Hz 1MHz, –148.5dBc/Hz 10MHz, –152.
PAGE 17
Data Sheet AD9525 –20 –20 –30 –40 –50 –60 –70 –80 1 2 –110 –120 –130 –140 –150 –160 –170 3 5 NOISE: ANALYSIS RANGE X: START 1kHz STOP 100MHz INTG NOISE: –62.1dBc/19.7MHz RMS NOISE: 1.1µRAD 63.6mdeg RMS JITTER: 86.2fsec –180 100 1k 10k 100k FREQUENCY (Hz) 7 4 –70 –80 –90 –100 1 –110 –120 2 –130 –140 5 3 –150 –160 6 4 7 6 –170 1M 10M 100M –180 100 Figure 16. Phase Noise (Absolute), External VCO 2.05 GHz VCO (Bowei Model MVCO-2050A); at 2050 MHz; Reference = 122.
PAGE 18
AD9525 Data Sheet TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.
PAGE 19
Data Sheet AD9525 DETAILED BLOCK DIAGRAM REF_SEL CP VDD_CP CP_RSET CLKIN CLKIN AD9525 REFA REFA REFB REFB REFC NINE DIFFERENTIAL OUTPUTS LVPECL ÷RA 1, 2, 3... 32 ÷RB 1, 2, 3... 32 PFD SYNC GENERATION CHARGE PUMP ÷S SYNC_OUT SYNC_OUT OUT7 ÷RC 1, 2, 3... 127 ÷M 1, 2, 3, 4, 5, 6 OUT7 OUT6 OUT6 OUT5 OUT5 SDIO OUT4 SDO CS OUT3 OUT3 ÷N RESET OUT2 ÷B 1, 2, 3...
PAGE 20
AD9525 Data Sheet THEORY OF OPERATION The AD9525 PLL is useful for generating clock frequencies from a supplied reference frequency. In addition, the PLL can be used to clean up jitter and phase noise on a noisy reference. The exact choice of PLL parameters and loop dynamics is application specific. The flexibility and depth of the AD9525 PLL allow the part to be tailored to function in many different applications and signal environments.
PAGE 21
Data Sheet AD9525 Reference Switchover M Divider The AD9525 supports two separate differential reference inputs. Manual switchover is performed between these inputs either through Register 0x01A or by using the REF_SEL pin. This feature supports networking and other applications that require redundant references. The M divider is a fixed divide (FD) of 1, 2, 3, 4, 5, or 6.
PAGE 22
AD9525 Data Sheet Digital Lock Detect (DLD) VCO CLKIN 50Ω CLKIN R2 CP R1 C3 C1 C2 AD9525 1VCO MANUFACTURERS RECOMMEND EITHER A T OR PI ATTENUATOR TO PREVENT VCO PULLING. REFER TO MANUFACTURER’S RECOMMENDATION A lock is not indicated until there is a programmable number of consecutive PFD cycles with a time difference that is less than the lock detect threshold.
PAGE 23
Data Sheet AD9525 ways to activate safe power-down mode: individually set the power-down bit for each driver, power down an individual output channel, or activate sleep mode. CLOCK DISTRIBUTION The AD9525 can be used only as a clock fan out buffer by disabling the PLL circuit blocks except for the clock distribution section. The clock distribution consists of eight LVPECL clock output drivers that share a common M divider. See the M Divider section for more information on the common M divider.
PAGE 24
AD9525 Data Sheet Single Shot Mode Pseudorandom Mode In single shot mode one sync pulse occurs after writing SYNC ENABLE 0x192[4] = 1. An IO_UPDATE is required to complete a register write. The width of the sync pulse is determined by the value of the S divider. A divider value of 0x0000 allows a pulse whose width is equal to one half period of the phase detector rate. A divider value of 0x0001 allows a pulse whose width is equal to two half periods of the phase detector rate.
PAGE 25
Data Sheet AD9525 SYNC_OUT CONTROL PROGRAM: S DIVIDER, SYNC MODE USER PROGRAMS REGISTER VALUE FOR S DIVIDER AND SYNC MODE PROGRAM: SYNC ENABLE REQUEST SYNC PROGRAM: IO UPDATE NO LOCK DETECT = HIGH YES DIGITAL LOCK DETECT IS USED TO PREVENT OCCURENCE OF SYNC IF PLL IS UNLOCKED THE ANALOG CLOCK TO THE DIGITAL STATE MACHINE IS DISABLED IF SYNC IS DISABLED ENABLE_ANALOG SYNC HIGH FOR S DIVIDER + 1 REF CLOCK CYCLES SYNC LOW SYNC ENABLE LOW? NO SYNC ENABLE IS SELF CLEARING IN SINGLE SHOT MODE.
PAGE 26
AD9525 Data Sheet POWER-DOWN MODES PLL Power-Down Chip Power-Down via PD The PLL section of the AD9525 can be selectively powered down. In this mode, the AD9525 can be used as a 1 to 8 clock buffer by using the CLKIN as the clock input. The AD9525 can be put into a power-down condition by pulling the PD pin low. Power-down turns off most of the functions and currents inside the AD9525. The chip remains in this power-down state until PD is brought back to logic high.
PAGE 27
Data Sheet AD9525 SERIAL CONTROL PORT The AD9525 serial control port is a flexible, synchronous serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9525 serial control port is compatible with most synchronous transfer formats, including Motorola® SPI and Intel® SSR protocols. The serial control port allows read/write access to all registers that configure the AD9525.
PAGE 28
AD9525 Data Sheet Read The AD9525 supports only the long instruction mode. If the instruction word is for a read operation, the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 3 as determined by [W1:W0]. If N = 4, the read operation is in streaming mode, continuing until CS is raised. Streaming mode does not skip over reserved or blank registers. The readback data is valid on the falling edge of SCLK.
PAGE 29
Data Sheet AD9525 Table 26. Serial Control Port, 16-Bit Instruction Word, MSB First MSB LSB I15 R/W I14 W1 I13 W0 I12 A12 = 0 I11 A11 = 0 I10 A10 = 0 I9 A9 I8 A8 I7 A7 I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 I0 A0 CS SCLK DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE 10011-029 SDIO DON'T CARE REGISTER (N – 1) DATA Figure 28.
PAGE 30
AD9525 Data Sheet tS tC CS tCLK tHIGH SCLK tLOW tDS SDIO BIT N BIT N + 1 Figure 33. Serial Control Port Timing—Write Table 27.
PAGE 31
Data Sheet AD9525 CONTROL REGISTERS CONTROL REGISTER MAP OVERVIEW When writing to registers with bits that are marked reserved, the user should take care to always write the default value for the reserved bits. Register addresses that are not listed in Table 28 are not used, and writing to those registers has no effect. Registers that are marked as reserved should never have their values changed. Table 28. Control Register Map Reg. Addr.
PAGE 32
AD9525 Data Sheet Reg. Addr.
PAGE 33
Data Sheet AD9525 REGISTER MAP DESCRIPTIONS Table 29 through Table 49 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Table 29. SPI Mode Serial Port Configuration Reg. Addr. (Hex) 0x000 0x004 Bits 7 Bit Name SDO active 6 LSB first/address increase 5 Soft reset 4 [3:0] Unused Mirror[7:4] 0 Read back active registers Description Selects unidirectional or bidirectional data transfer mode.
PAGE 34
AD9525 Data Sheet Table 31. REFA, REFB, REFC, B, N, and P Dividers Reg. Addr.
PAGE 35
Data Sheet Reg. Addr. (Hex) 0x016 Bits 2 Bit Name REFB divider reset 1 REFA divider reset 0 Reset all dividers 7 REFC enable [6:0] REFC divider AD9525 Description Resets REFB divider. 0: normal (default). 1: holds REFB divider in reset. Resets REFA divider. 0: normal (default). 1: holds REFA divider in reset. Resets REFA, REFB, B divider (B divider is part of N divider). 0: normal (default). 1: holds REFA, REFB, B divider in reset. Enables REFC path. 0: disabled (default). 1: enables REFC path.
PAGE 36
AD9525 Reg. Addr.
PAGE 37
Data Sheet AD9525 Table 33. REF_MON Pin Control Reg. Addr. (Hex) 0x018 Bits [7:5] [4:0] Bit Name Don’t care REF_MON pin control Description Don’t care. Selects the signal that is connected to the REF_MON pin. Level or Dynamic Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Signal Signal at REF_MON Pin 0 0 0 0 0 LVL Ground (dc). 0 0 0 0 1 DYN REFA clock. 0 0 0 1 0 DYN REFB clock. 0 0 0 1 1 DYN Selected reference clock to PLL. 0 0 1 0 0 DYN Unselected reference clock to PLL.
PAGE 38
AD9525 Data Sheet Table 34. Lock Detect Reg. Addr. (Hex) 0x019 Bits [7:4] [3:2] Bit Name Don’t care Lock detect counter 1 Digital lock detect window 0 Digital lock detect disable Description Don’t care. Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked condition.
PAGE 39
Data Sheet AD9525 Table 36. Reserved Reg. Addr. (Hex) 0x01B Bits [7:0] Bit Name Reserved Description Reserved. 0: default. All bits should be set to 0. Table 37. PLL Block Power-Down Reg. Addr.
PAGE 40
AD9525 Data Sheet Table 38. PLL Readback Reg. Addr.
PAGE 41
Data Sheet AD9525 Table 41. LVPECL Drivers OUT2 Reg. Addr. (Hex) 0x0F2 Bits [7:5] 4 Bit Name Don’t care Power down Channel 2 and Channel 3 3 [2:1] Don’t care OUT2 level 0 OUT2 driver power-down Description Don’t care Powers down Channel 2 and Channel 3 0: enabled (default) 1: power-down Don’t care Bit 1 Bit 0 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0: enabled (default) 1: power-down Table 42. LVPECL Drivers OUT3 Reg. Addr.
PAGE 42
AD9525 Data Sheet Table 44. LVPECL Drivers OUT5 Reg. Addr. (Hex) 0x0F5 Bits [7:5] 4 3 [2:1] Bit Name Don’t care Reserved Don’t care OUT5 level 0 OUT5 driver power-down Description Don’t care Reserved, write 0 Don’t care Bit 1 Bit 0 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 0: enabled (default) 1: power-down Table 45. LVPECL Drivers OUT6 Reg. Addr.
PAGE 43
Data Sheet AD9525 Table 47. SYNC_OUT Control Reg. Addr. (Hex) 0x0F8 Bits [7:5] 4 3 0x0F9 Bit Name Don’t care SYNC_OUT channel power-down Sync polarity [2:1] SYNC_OUT level 0 SYNC_OUT driver power-down Don’t care Polarity CMOS mode [7:5] 4 [3:2] Enable CMOS drivers 1 CMOS mode 0 Sync out resampling edge select Sync clock S divider 0x190 [7:0] 0x191 [7:0] 0x192 [7:5] 4 Sync clock S divider Don’t care Sync enable [3:2] Sync source [1:0] Sync mode Description Don’t care.
PAGE 44
AD9525 Data Sheet Table 48. VCO, Reference, and CLK Inputs Reg. Addr. (Hex) 0x1E0 Bits [7:3] [2:0] Bit Name Don’t care M divider Description Don’t care. M divider value. Bit 2 Bit 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Bit 0 0 1 0 1 0 1 0 1 Divider Value 1 2 3 4 5 6 7 8 Table 49. Other Reg. Addr.
PAGE 45
Data Sheet AD9525 APPLICATIONS INFORMATION 18 16 90 80 70 60 tJ = 100 fs tJ = 200 fs tJ = 400 fs tJ = 1ps tJ = 2ps 14 12 10 50 Choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current and, thus, allows the designer to fine-tune the PLL loop bandwidth in either direction. 40 tJ = 10p 8 s 6 30 10 100 fA (MHz) 1k Figure 34. SNR and ENOB vs.
PAGE 46
AD9525 Data Sheet LVPECL CLOCK DISTRIBUTION SYNC_OUT DISTRIBUTION The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 22 shows the LVPECL output stage. The SYNC_OUT driver of the AD9525 can be configured as CMOS drivers. When selected for use as CMOS drivers, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as inverting or noninverting.
PAGE 47
Data Sheet AD9525 OUTLINE DIMENSIONS 0.30 0.23 0.18 PIN 1 INDICATOR 48 37 36 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 5.20 5.10 SQ 5.00 EXPOSED PAD 12 25 24 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. 112408-B 7.00 BSC SQ Figure 40.