Datasheet

AD9549
Rev. D | Page 15 of 76
Figure 12. HSTL Output Driver Single-Ended Peak-to-Peak Amplitude vs.
Toggle Rate (100 Ω Across Differential Pair)
Figure 13. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate
(AVDD3 = 1.8 V) with 20 pF Load
Figure 14. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate
(AVDD3 = 3.3 V) with 20 pF Load
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0 0.5 1.0 1.5 2.0 2.5
TIME (ns)
0.4
0.6
0.2
0
–0.2
–0.4
–0.6
AMPLITUDE (V)
FREQUENCY= 600MHz
T
RISE
(20→80%) = 104ps
T
FALL
(80→20%) = 107ps
V p-p = 1.17V DIFF.
DUTY CYCLE = 50%
Figure 15. Typical HSTL Output Waveform, Nominal Conditions,
DC-Coupled, Differential Probe Across 100 Ω load
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0 20 40 60 80 100
TIME (ns)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
AMPLITUDE (V)
FREQUENCY= 20MHz
T
RISE
(20→80%) = 5.5ns
T
FALL
(80→20%) = 5.9ns
V p-p = 1.8V
DUTY CYCLE = 53%
Figure 16. Typical CMOS Output Driver Waveform (@ 1.8 V),
Nominal Conditions, Estimated Capacitance: 5 pF
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0 10 20 30 40 50
TIME (ns)
3.3
2.8
2.3
1.8
1.3
0.8
0.3
–0.2
AMPLITUDE (V)
FREQUENCY= 40MHz
T
RISE
(20→80%) = 2.25ns
T
FALL
(80→20%) = 2.6ns
V p-p = 3.3V
DUTY CYCLE = 52%
Figure 17. CMOS Output Driver Waveform (@ 3.3 V), Nominal Conditions,
Estimated Capacitance: 5 pF, f
OUT
= 20 MHz