Datasheet

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Oscillator Frequency Upconverter

Data Sheet

AD9552

Rev. E Document Feedback

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FEATURES

Converts a low frequency input reference signal to a high

frequency output signal

Input frequencies from 6.6 MHz to 112.5 MHz

Output frequencies up to 900 MHz

Preset pin programmable frequency translation ratios

Arbitrary frequency translation ratios via SPI port

On-chip VCO

Accepts a crystal resonator and/or an external oscillator

as a reference frequency source

Secondary output (either integer-related to the primary

output or a copy of the reference input)

RMS jitter: <0.5 ps

SPI-compatible, 3-wire programming interface

Single supply (3.3 V)

Very low power: <400 mW (under most conditions)

Small package size (5 mm × 5 mm)

APPLICATIONS

Cost effective replacement of high frequency VCXO, OCXO,

and SAW resonators

Extremely flexible frequency translation with low jitter for

SONET/SDH (including FEC), 10 Gb Ethernet, Fibre

Channel, and DRFI/DOCSIS

High-definition video frequency translation

Wireless infrastructure

Test and measurement (including handheld devices)

GENERAL DESCRIPTION

The AD9552 is a fractional-N phase locked loop (PLL) based

clock generator designed specifically to replace high frequency

crystal oscillators and resonators. The device employs a sigma-

delta (Σ-Δ) modulator (SDM) to accommodate fractional

frequency synthesis. The user supplies an input reference signal

by connecting a single-ended clock signal directly to the REF

pin or by connecting a crystal resonator across the XTAL pins.

The AD9552 is pin programmable, providing one of 64 standard

output frequencies based on one of eight common input

frequencies. The device also has a 3-wire SPI interface, enabling

the user to program custom input-to-output frequency ratios.

The AD9552 relies on an external capacitor to complete the loop

filter of the PLL. The output is compatible with LVPECL, LVDS,

or single-ended CMOS logic levels, although the AD9552 is

implemented in a strictly CMOS process.

The AD9552 is specified to operate over the extended industrial

temperature range of −40°C to +85°C.

BASIC BLOCK DIAGRAM

PLL

OUTPUT

CIRCUITRY

INPUT

FREQUENCY

SOURCE

SELECTOR

REF

TAL

OUT2

OUT1

PIN-DEFINED AND SERIAL PROGRAMMING

AD9552

07806-001

Figure 1.

Summary of content (32 pages)

PAGE 1
Oscillator Frequency Upconverter AD9552 Data Sheet FEATURES GENERAL DESCRIPTION Converts a low frequency input reference signal to a high frequency output signal Input frequencies from 6.6 MHz to 112.
PAGE 2
AD9552 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Preset Frequency Ratios ............................................................ 13 Applications ....................................................................................... 1 Component Blocks ..................................................................... 15 General Description ...............................................................
PAGE 3
Data Sheet AD9552 SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for VDD = 3.3 V; TA = 25°C, unless otherwise noted. Table 1.
PAGE 4
AD9552 Parameter Input Capacitance Input Resistance Duty Cycle Input Voltage Input High Voltage, VIH Input Low Voltage, VIL Input Threshold Voltage Data Sheet Min 40 Max 60 1.62 Unit pF kΩ % 1.0 V V V 4050 3350 45 MHz MHz MHz/V 140 ppm μs 0.52 VCO CHARACTERISTICS Frequency Range Upper Bound Lower Bound VCO Gain VCO Tracking Range VCO Calibration Time Typ 3 130 ±300 Test Conditions/Comments When ac coupling to the input receiver, the user must dc bias the input to 1 V fPFD 7 = 77.
PAGE 5
Data Sheet Parameter LVDS MODE Differential Output Voltage Swing Balanced, VOD AD9552 Min Typ 247 Unbalanced, ΔVOD Offset Voltage Common Mode, VOS Common-Mode Difference, ΔVOS 1.125 Short-Circuit Output Current Frequency Range Duty Cycle Rise/Fall Time1 (20% to 80%) 0 40 17 285 Max Unit Test Conditions/Comments 454 mV 25 mV Voltage swing between output pins; output driver static Absolute difference between voltage swing of normal pin and inverted pin; output driver static 1.
PAGE 6
AD9552 Data Sheet SERIAL CONTROL PORT Table 5. Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO Input Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance Output Output Logic 1 Voltage Output Logic 0 Voltage Min Typ Max 1.6 0.5 0.03 2 2 1.6 0.5 2 0.03 2 1.6 0.
PAGE 7
Data Sheet AD9552 ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 7. Parameter Supply Voltage (VDD) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 3.6 V −0.5 V to VDD + 0.5 V −65°C to +150°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 8
AD9552 Data Sheet 32 31 30 29 28 27 26 25 Y3 Y2 Y1 Y0 VDD OUT1 OUT1 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD9552 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 GND OUT2 OUT2 VDD LOCKED LDO VDD LDO NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND. 07806-002 XTAL XTAL REF CS SCLK SDIO OUTSEL FILTER 9 10 11 12 13 14 15 16 Y4 Y5 A0 A1 A2 RESET VDD LDO Figure 2. Pin Configuration Table 8. Pin Function Descriptions Pin No.
PAGE 9
Data Sheet AD9552 TYPICAL PERFORMANCE CHARACTERISTICS –30 –40 –50 –50 –60 –70 –60 –70 –80 –90 –100 –110 –120 –130 –140 –80 –90 –100 –110 –120 –130 –140 –150 –150 –160 –170 –180 100 –160 –170 –180 100 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 3. Phase Noise, Fractional-N, Pin Programmed (fXTAL = 19.44 MHz, fOUT1 = 625 MHz) CARRIER 624.999995MHz 0.4057dBm –50 –50 –60 –70 –60 –70 PHASE NOISE (dB) –30 –40 –80 –90 –100 –110 –120 –130 –140 –130 –140 –160 –170 –180 100 100M Figure 4.
PAGE 10
AD9552 Data Sheet 1.6 25 LVPECL 1.4 AMPLITUDE (V p-p) 15 10 1.2 LVDS (STRONG) 1.0 0.8 LVDS (WEAK) 5 0.6 0 50 100 150 FREQUENCY (MHz) 200 250 0.4 07806-020 0 0 Figure 9. Supply Current vs. Output Frequency, CMOS (15 pF Load) 200 400 600 FREQUENCY (MHz) 800 1000 07806-023 SUPPLY CURRENT (mA) 20 Figure 12. Peak-to-Peak Output Voltage vs. Frequency, LVPECL and LVDS (15 pF Load) 4.0 60 3.5 5pF 10pF DUTY CYCLE (%) AMPLITUDE (V p-p) 3.0 2.5 20pF 2.0 1.5 55 1.
PAGE 11
AD9552 1.25ns/DIV Figure 15. Typical Output Waveform, LVDS (805 MHz, 3.5 mA Drive Current) Figure 16. Typical Output Waveform, CMOS (250 MHz, 15 pF Load) Rev.
PAGE 12
AD9552 Data Sheet INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.1µF AD9552 3.3V DIFFERENTIAL OUTPUT (LVDS OR LVPECL MODE) DOWNSTREAM DEVICE 07806-028 0.1µF Figure 17. AC-Coupled LVDS or LVPECL Output Driver DOWNSTREAM DEVICE Figure 18. DC-Coupled LVDS or LVPECL Output Driver Rev. E | Page 12 of 32 07806-029 HIGH IMPEDANCE INPUT 100Ω AD9552 100Ω 3.
PAGE 13
Data Sheet AD9552 THEORY OF OPERATION LOCKED DETECTOR FILTER AD9552 LOCK DETECT 2 REFA XTAL 2× PFD Y5:0 VCO P0 P1 2 OUT1 N1 4 OR 5 Σ-Δ MODULATOR 3 REGISTER BANK N MOD, FRAC 3 6 PRECONFIGURED DIVIDER VALUES P0, P1 N, MOD, FRAC, P0, P1 07806-006 A2:0 1 TO 63 N = 4N1 + N0 XTAL SERIAL PORT 4 TO 11 CHARGE PUMP TUNING CONTROL OUT2 3350MHz TO 4050MHz Figure 19.
PAGE 14
AD9552 Data Sheet Table 10.
PAGE 15
Data Sheet Y5 1 1 1 1 1 1 1 1 1 1 Y4 1 1 1 1 1 1 1 1 1 1 AD9552 Y3 0 0 1 1 1 1 1 1 1 1 Y2 1 1 0 0 0 0 1 1 1 1 Y1 1 1 0 0 1 1 0 0 1 1 Y0 0 1 0 1 0 1 0 1 0 1 VCO Frequency (MHz) 3536.763 3582.686 3593.75 3598.672 3740.355 3750 3888 3897.843 3906.25 4028.32 Output (MHz) 657.421875 × (255/237) 716.5372 718.75 719.7344 748.0709 750 777.6 779.5686 781.
PAGE 16
AD9552 Data Sheet The gain of the PLL is proportional to the current delivered by the charge pump. The user can override the default charge pump current setting, and, thereby, the PLL gain, by using Register 0x0A[7:0]. The PLL has a VCO with 128 frequency bands spanning a range of 3350 MHz to 4050 MHz (3700 MHz nominal). However, the actual operating frequency within a particular band depends on the control voltage that appears on the loop filter capacitor.
PAGE 17
Data Sheet AD9552 PART INITIALIZATION AND AUTOMATIC POWERON RESET The AD9552 has an internal power-on reset circuit. At power-up, internal logic relies on the internal reference monitor to select either the crystal oscillator or the reference input and then initiates VCO calibration using whichever is found. If both are present, the external reference path is chosen. VCO calibration is required in order for the device to lock.
PAGE 18
AD9552 Data Sheet It is imperative that long division be used to obtain the correct results. Avoid the use of a calculator or math program, because these do not always yield correct results due to internal rounding and/or truncation. Some calculators or math programs may be up to the task if they can handle very large integer operations, but such are not common. Table 12.
PAGE 19
Data Sheet AD9552 APPLICATIONS INFORMATION THERMAL PERFORMANCE Table 13. Thermal Parameters for the 32-Lead LFCSP Package Symbol θJA θJMA θJMA θJB θJC ΨJT 1 2 Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board 1 Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
PAGE 20
AD9552 Data Sheet SERIAL CONTROL PORT The AD9552 serial control port is a flexible, synchronous, serial communications port that allows an easy interface to many industry-standard microcontrollers and microprocessors. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9552 serial control port is configured for a single bidirectional I/O pin (SDIO only). The serial control port has two types of registers: read-only and buffered.
PAGE 21
Data Sheet AD9552 MSB/LSB FIRST TRANSFERS SDIO 14 CS SERIAL CONTROL PORT 12 REGISTER UPDATE EXECUTE AN INPUT/OUTPUT UPDATE The AD9552 instruction word and byte data can be MSB first or LSB first. The default for the AD9552 is MSB first. The LSB first mode can be set by writing a 1 to Register 0x00[6] and requires that an I/O update be executed. Immediately after the LSB first bit is set, all serial control port operations are changed to LSB first order.
PAGE 22
AD9552 Data Sheet CS SCLK DON'T CARE A6 A5 A7 R/W W1 W0 A12 A11 A10 A9 A8 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D7 D0 REGISTER (N) DATA D6 D5 D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 07806-008 SDIO DON'T CARE DON'T CARE Figure 24.
PAGE 23
Data Sheet AD9552 REGISTER MAP A bit that is labeled “aclr” is an active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns it to a Logic 0 state upon completion of the indicated task. Table 17. Register Map Addr.
PAGE 24
AD9552 Addr.
PAGE 25
Data Sheet AD9552 PLL Charge Pump and PFD Control (Register 0x0A to Register 0x0D) Table 19.
PAGE 26
AD9552 Data Sheet VCO Control (Register 0x0E to Register 0x10) Table 20. Address 0x0E Bit 7 6 Bit Name Calibrate VCO Enable ALC [5:3] ALC threshold 2 Enable SPI control of VCO calibration 1 Boost VCO supply 0 Enable SPI control of VCO band setting 0x0F [7:2] VCO level control 0x10 [1:0] [7:1] Unused VCO band control 0 Unused 1 Description Initiates VCO calibration (this is an autoclearing bit). This bit is ineffective unless Bit 2 = 1. Enables automatic level control (ALC) of the VCO.
PAGE 27
Data Sheet Address 0x18 0x19 AD9552 Bit [7:3] Bit Name P1 divider [2:0] P0 divider 7 Enable SPI control of OUT1 dividers [6:0] Unused Description Bits[4:0] of the 6-bit P1 divider for OUT1 (1 ≤ P1 ≤ 63). Do not set these bits to 000000. Default is P1 = 10 0000 (32). The P1 bits are ineffective unless Register 0x19[7] = 1. The 3-bit P0 divider for OUT1. The P0 divide value is as follows: 000 = 4 (default). 001 = 5. 010 = 6. 011 = 7. 100 = 8. 101 = 9. 110 = 10. 111 = 11.
PAGE 28
AD9552 Data Sheet OUT1 Driver Control (Register 0x32) Table 24. Address 0x32 Bit 7 Bit Name OUT1 drive strength 6 OUT1 power-down [5:3] OUT1 mode control [2:1] OUT1 CMOS polarity 0 Enable SPI control of OUT1 driver control Description Controls the output drive capability of the OUT1 driver. 0 = weak. 1 = strong (default). Controls power-down functionality of the OUT1 driver. 0 = OUT1 active (default). 1 = OUT1 powered down. OUT1 driver mode selection. 000 = CMOS, both pins active.
PAGE 29
Data Sheet AD9552 OUT2 Driver Control (Register 0x34) Table 26. Address 0x34 Bit 7 Bit Name OUT2 drive strength 6 OUT2 power-down [5:3] OUT2 mode control [2:1] OUT2 CMOS polarity 0 Enable SPI control of OUT2 driver control Description Controls the output drive capability of the OUT2 driver. 0 = weak. 1 = strong (default). Controls power-down functionality of the OUT2 driver. 0 = OUT2 active (default). 1 = OUT2 powered down. OUT2 driver mode selection. 000 = CMOS, both pins active.
PAGE 30
AD9552 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 30.
PAGE 31
Data Sheet AD9552 NOTES Rev.