Datasheet

AD9553
Rev. A | Page 38 of 44
Input Receiver and Band Gap Control (Register 0x1A)
Table 32.
Address Bit Bit Name Description
0x1A 7 Receiver reset Input receiver reset control. This is an autoclearing bit.
0 = normal operation (default).
1 = resets the reference input hardware (detectors, dividers, switchover control,
crystal oscillator, and its associated frequency doubler).
[6:2] Band gap voltage adjust Controls the band gap voltage setting from minimum (00000) to maximum (11111).
Default is 00000.
The band gap voltage adjust bits are ineffective unless Register 0x1A[0] = 1.
1 Unused Unused.
0 Enable SPI control of band
gap voltage
Enables functionality of Register 0x1A[6:2].
0 = the device automatically selects receiver band gap voltage (default).
1 = Register 0x1A[6:2] defines the receiver band gap voltage.
XTAL Control (Register 0x1B to Register 0x1E)
Table 33.
Address Bit Bit Name Description
0x1B 7 Disable SPI control of XTAL
tuning capacitance
Disables functionality of Register 0x1B[5:0].
0 = tuning capacitance defined by Register 0x1B[5:0].
1 = the device automatically selects XTAL tuning capacitance (default).
6 Unused When programming this register write a Logic 0 to this bit.
[5:0] XTAL tuning capacitor control Capacitance value coded as inverted binary (0.25 pF per bit); that is, 111111 is 0 pF,
111110 is 0.25 pF, and so on. The default value, 000000, is 15.75 pF. The XTAL tuning
capacitor bits are ineffective unless Register 0x1B[7] = 0.
0x1C [7:0] Unused Unused.
0x1D [7:0] Unused Unused.
0x1E [7:0] Unused Unused.
REFA Frequency Control (Register 0x1F to Register 0x22)
Table 34.
Address Bit Bit Name Description
0x1F [7:0] REFA divider (R
A
) Bits[13:6] of the 14-bit REFA divider.
0x20 [7:2] REFA divider (R
A
)
Bits[5:0] of the 14-bit REFA divider (default: R
A
= 4096 decimal). The REFA divider bits
are ineffective unless Register 0x20[1] = 1.
1 Enable SPI control of R
A
Enables SPI port control of the REFA divider value (R
A
).
0 = the A3 to A0 pins define R
A
per Table 14 (default).
1 = the 14-bit value in the REFA divider register defines R
A
.
0 Unused Unused.
0x21 7 Enable SPI control of ×2
A
Enables SPI control of the REFA ×2 frequency multiplier (×2
A
) per 0x21[6].
0 = the device automatically selects ×2
A
per Table 14 (default).
1 = Register 0x21[6] controls the selection of ×2
A
.
6 Select ×2
A
Selects ×2
A
. This bit is ineffective unless Register 0x21[7] = 1.
0 = bypass ×2
A
(default).
1 = select ×2
A
.
5 Enable SPI control of ÷5
A
Enables SPI control of the ÷5
A
prescaler per 0x21[4].
0 = the device automatically selects ÷5
A
per Table 14 (default).
1 = Register 0x21[4] controls the selection of ÷5
A
.
4 Select ÷5
A
Selects ÷5
A
. This bit is ineffective unless Register 0x21[5] = 1.
0 = bypass ÷5
A
(default)
1 = select ÷5
A
.
[3:0] Unused Unused.
0x22 [7:0] Unused Unused.