Datasheet

AD9557 Data Sheet
Rev. B | Page 18 of 92
Pin No. Mnemonic
Input/
Output Pin Type Description
15
A
OUT0
E O HSTL, LVDS,
1.8 V CMOS,
3.3 V CMOS
Complementary Output 0. This output can be configured as HSTL, LVDS, or
single-ended 1.8 V or 3.3 V CMOS.
16
OUT0 O HSTL, LVDS,
1.8 V CMOS,
3.3 V CMOS
Output 0. This output can be configured as HSTL, LVDS, or single-ended 1.8 V
or 3.3 V CMOS. LVPECL levels can be achieved by ac coupling and using the
Thevenin-equivalent termination as described in the Input/Output Termination
Recommendations section.
20
LDO_VCO2 I LDO bypass Output PLL Loop Filter Voltage Regulator. Connect a 0.47 μF capacitor from this
pin to ground. This pin is also the ac ground reference for the integrated output
PLL external loop filter.
21
LF_VCO2 I/O Loop filter Loop Filter Node for the Output PLL. Connect an external 6.8 nF capacitor from
this pin to Pin 20 (LDO_VCO2).
25
A
RESET
E
I 3.3 V CMOS Chip Reset. When this active low pin is asserted, the chip goes into reset.
This pin has an internal 50 kΩ pull-up resistor.
26 PINCONTROL I 3.3 V CMOS Pin Program Mode Enable Pin. When pulled high during startup, this pin enables
pin programming of the AD9557 configuration during startup. If this pin is low
during startup, the user must program the part via the serial port or use values
that are stored in the EEPROM.
27
A
SYNC
E
I 3.3 V CMOS Clock Distribution Synchronization Pin. When this pin is activated, output drivers
are held static and then synchronized on a low-to-high transition of this pin. This
pin has an internal 60 kΩ pull-up resistor.
28
REFA I Differential
input
Reference A Input. This internally biased input is typically ac-coupled and, when
configured as such, can accept any differential signal with single-ended swing up
to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.
29
A
REFA
E
I Differential
input
Complementary Reference A Input. This pin is the complementary input to Pin
28.
30, 31, 40
DVDD3 I Power 3.3 V Digital Power Supply.
32
REFB I Differential
input
Reference B Input. This internally biased input is typically ac-coupled and, when
configured as such, can accept any differential signal with single-ended swing up
to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.
33
A
REFB
E I Differential
input
Complementary Reference B Input. This pin is the complementary input to Pin 32.
36, 37, 38,
39
M0, M1, M2,
M3
I/O 3.3 V CMOS
(3-level logic
at startup)
Configurable I/O Pins. These pins are 3-level logic at startup and are used for pin
strapping the input and output frequency configuration at startup. Setting
Register 0x0200[0] = 1 changes these pins to 2-level logic and allows these pins
to be used for status and control of the AD9557. These pins have both a 30 kΩ
pull-up resistor and a 30 kΩ pull-down resistor.
EP VSS O Exposed pad The exposed pad must be connected to ground (VSS).