Datasheet

Data Sheet AD9557
Rev. B | Page 27 of 92
Program the Digital Phase-Locked Loop (DPLL)
The DPLL parameters reside in Register 0x0300 to
Register 0x032E. They include the following:
• Free run frequency
• DPLL pull-in range limits
• DPLL closed-loop phase offset
• Phase slew control (for hitless reference switching)
• Tuning word history control (for holdover operation)
Program the Reference Inputs
The reference input parameters reside in Register 0x0600 to
Register 0x0602. See the Reference Clock Input section for
details on programming these functions. They include the
following:
• Reference power-down
• Reference logic family
• Reference priority
Program the Reference Profiles
The reference profile parameters reside in Register 0x0700 to
Register 0x0766. The AD9557 evaluation software contains
a wizard that calculates these values based on the user’s input
frequency. See the Reference Profiles section for details on
programming these functions. They include the following:
• Reference period
• Reference period tolerance
• Reference validation timer
• Selection of high phase margin, loop filter coefficients
• DPLL loop bandwidth
• Reference prescaler (R divider)
• Feedback dividers (N1, N2, N3, FRAC1, and MOD1)
• Phase and frequency lock detector controls
Generate the Reference Acquisition
After the registers are programmed, the user can clear the user
freerun bit (Register 0x0A01[5]) and issue an I/O update, using
Register 0x0005[0] to invoke all of the register settings that are
programmed up to this point.
After the registers are programmed, the DPLL locks to the first
available reference that has the highest priority.