Datasheet

AD9557 Data Sheet
Rev. B | Page 36 of 92
CLOCK DISTRIBUTION
RF DIV 1
÷3 TO ÷11
FROM DPLL
(3.35GHz TO 4.05GHz)
RF DIV 2
÷3 TO ÷11
CHIP RESET
SYNC
÷M0
÷M1
10-BIT INTEGER
360kHz TO 1250MHz
10-BIT INTEGER
CHANNEL
SYNC
BLOCK
MAX
1.25GHz
MAX
1.25GHz
CHANNEL
SYNC
(TO M0 AND M1)
OUT0
OUT0
OUT1
OUT1
09197-139
Figure 40. Clock Distribution Block Diagram
A diagram of the clock distribution block appears in Figure 40.
CLOCK DIVIDERS
The channel divider blocks, M0 and M1, are 10-bit integer
dividers with a divide range of 1 to 1023. The channel divider
block contains duty cycle correction that guarantees 50% duty
cycle for both even and odd divide ratios.
OUTPUT POWER-DOWN
The output drivers can be individually powered down.
OUTPUT ENABLE
Each of the output channels offers independent control of enable/
disable functionality via the distribution enable register. The
distribution outputs use synchronization logic to control
enable/disable activity to avoid the production of runt pulses
and ensure that outputs with the same divide ratios become
active/inactive in unison.
OUTPUT MODE
The user has independent control of the operating mode of each
of the four output channels via the output clock distribution
registers (Address 0x0500 to Address 0x0509). The operating
mode control includes
 Logic family and pin functionality
 Output drive strength
 Output polarity
 Divide ratio
 Phase of each output channel
OUT0 provides 3.3 V CMOS, in addition to 1.8 V CMOS
modes. OUT1 has 1.8 V CMOS, LVDS, and HSTL modes.
All CMOS drivers feature a CMOS drive strength that allows
the user to choose between a strong, high performance CMOS
driver, or a lower power setting with less EMI and crosstalk.
The best setting is application dependent.
For applications where LVPECL levels are required, the user
should choose the HSTL mode, and ac-couple the output signal.
See the Input/Output Termination Recommendations section
for recommended termination schemes.
CLOCK DISTRIBUTION SYNCHRONIZATION
Divider Synchronization
The dividers in the clock distribution channels can be synchronized
with each other.
At power-up, the clock dividers are held static until a sync signal is
initiated by the channel SYNC block. The following are possible
sources of a SYNC signal, and these settings are found in
Register 0x0500:
 Direct sync via Bit 2 of Register 0x0500
 Direct sync via a sync op code (0xA1) in the EEPROM
storage sequence during EEPROM loading
 DPLL phase or frequency lock
 A rising edge of the selected reference input
 The
SYNC
pin
 A multifunction pin configured for the SYNC signal
The APLL lock detect signal gates the SYNC signal from the
channel SYNC block shown in Figure 40. The channel dividers
receive a SYNC signal from the channel SYNC block only if the
APLL is calibrated and locked, unless the APLL locked controlled
sync bit (Register 0x0405[3]) is set.
A channel can be programmed to ignore the sync function by
setting the mask Channel 1 sync and mask Channel 0 sync bits
(Bits[5:4]) in Register 0x0500. When programmed to ignore the
sync, the channel ignores both the user initiated sync signal and
the zero delay initiated sync signals, and the channel divider starts
toggling, provided that the APLL is calibrated and locked, or if
Bit 3 (APLL locked controlled sync bit), Register 0x0405, is set.
If the output SYNC function is to be controlled using an M pin,
use the following steps:
1. First, enable the M pins by writing Register 0x0200 = 0x01.
2. Issue an I/O update (Register 0x0005 = 0x01).
3. Set the appropriate M pin function.
If this process is not followed, a SYNC pulse is issued
automatically.