Datasheet

Data Sheet AD9557
Rev. B | Page 55 of 92
Freq ID Frequency (MHz) Frequency Description
Hard Pin Program
PINCONTROL = High
Soft Pin Program
PINCONTROL = Low,
Register 0x0C01[7:4]
M3 Pin
M2 Pin M1 Pin B7 B6 B5 B4
13
693.4830 644.53125 MHz × 255/237 ½ ½ ½ 1 1 0 1
14 698.8124 622.08 MHz × 255/237 ½ ½ 1 1 1 1 0
15
704.380580 657.421875 MHz × 255/238 ½ 1 0 1 1 1 1
Table 34. System Clock Configuration in Hard Pin and Soft Pin Programming Modes
Freq ID Frequency (MHz) System Clock Configuration
Hard Pin Program
PINCONTROL = High,
IRQ Pin
Soft Pin Program
PINCONTROL = Low,
Register 0x0C02[1:0]
Equivalent
System Clock
PLL Register
Settings
IRQ Pin
Bit 1 Bit 0
0
49.152 XTAL mode, doubler on, N = 8 0 0 0 0001, 0000, 1000
1
49.152 XTAL mode off, doubler on, N = 8 ½ 0 1
2 24.576 XTAL mode, doubler on, N = 16 1 1 0
3
98.304 XTAL mode off, doubler off, N = 8 N/A 1 1
HARD PIN PROGRAMMING MODE
The state of the PINCONTROL pin at power-up controls
whether or not the chip is in hard pin programming mode.
Setting the PINCONTROL pin high disables the I
2
C protocol,
although the register map can be accessed via the SPI protocol.
The M0 pin selects one of three input frequencies, and the
M3 to M1 pins select one of 16 possible output frequencies.
See Table 32 and Table 33 for details.
The system clock configuration is controlled by the state of
the IRQ pin at startup (see Table 34).
The digital PLL loop
bandwidth, reference input frequency accuracy tolerance
ranges, and DPLL phase margin selection are not available
in hard pin programming mode unless the user uses the
serial port to change their default values.
When in hard pin programming mode, the user must set
Register 0x0200[0] = 1 to activate the IRQ, REF status, and
PLL lock status signals at the multifunction pins.
SOFT PIN PROGRAMMING MODE OVERVIEW
The soft pin programming function is controlled by a dedicated
register section (Address 0x0C00 to Address 0x0C08). The
purpose of soft pin programming is to use the register bits to
mimic the hard pins for the configuration section. When in
soft pin programming mode, both the SPI and I
2
C ports are
available.
• Address 0x0C00[0] enables accessibility to Address
0x0C01 and Address 0x0C02 (Soft Pin Section 1). This
bit must be set in soft pin mode.
• Address 0x0C03[0] enables accessibility to Address 0x0C04
to Address 0x0C06 (Soft Pin Section 2). This bit must be
set in soft pin mode.
• Address 0x0C01[3:0] select one of 16 input frequencies.
• Address 0x0C01[7:4] select one of 16 output frequencies.
• Address 0x0C02[1:0] select the system clock configuration.
• Address 0x0C06[1:0] select one of four input frequency
tolerance ranges.
• Address 0x0C06[3:2] select one of four DPLL loop
bandwidths.
• Address 0x0C06[4] selects the DPLL phase margin.
• Address 0x0C04[3:0] scale the REFA and REFB input
frequency down by divide-by-1, -4, -8, or -16 independently.
For example, when Address 0x0C01[3:0] = 0101 to select
622.08 MHz input frequency for both REFA and REFB,
setting Address 0x0C04[1:0] = 0x01 scales down the REFA
input frequency to 155.52 MHz (= 622.08 MHz/4). This is
done by internally scaling the R divider for REFA up by
4× and the REFA period up by 4×.
• Address 0x0C05[3:0] scale the Channel 0 and Channel 1
output frequency down by divide-by-1, divide-by-4,
divide-by-8, or divide-by-16.