Datasheet

AD9557 Data Sheet
Rev. B | Page 62 of 92
Reg
Addr
(Hex)
Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def
0x07DC Reserved 00
0x07DD Reserved 00
0x07DE Reserved BC
0x07DF Reserved 02
0x07E0 Reserved 0A
0x07E1 Reserved 0A
0x07E2 Reserved BC
0x07E3 Reserved 02
0x07E4 Reserved 00
0x07E5 Reserved 0A
0x07E6 Reserved 0A
Operational Controls
0x0A00 Power-down Soft reset
exclude
regmap
DCO PD SYSCLK PD Ref input
PD
TDC PD APLL PD Clock dist
PD
Full PD 00
0x0A01 Loop mode Reserved User
holdover
User freerun REF switchover mode[2:0] Reserved User ref in
manual
switchover
mode
00
0x0A02
Cal/sync
Reserved
Soft sync
clock dist
Reserved
00
0x0A03 A Clear/reset
functions
Reserved Clear LF Clear CCI Reserved Clear auto
sync
Clear TW
history
Clear all
IRQs
Clear
watchdog
00
0x0A04 A IRQ clearing Reserved SYSCLK
unlocked
SYSCLK
locked
APLL
unlocked
APLL locked APLL cal
ended
APLL cal
started
00
0x0A05 A Reserved Pin program
end
Sync
clock dist
Watchdog
timer
EEPROM
fault
EEPROM
complete
00
0x0A06 A Switching Closed Freerun Holdover Frequency
unlocked
Frequency
locked
Phase
unlocked
Phase
locked
00
0x0A07 A Reserved History
updated
Frequency
unclamped
Frequency
clamped
Phase slew
unlimited
Phase slew
limited
00
0x0A08 A Reserved REFB
validated
REFB fault
cleared
REFB fault Reserved REFA
validated
REFA fault
cleared
REFA fault 00
0x0A09 A Reserved Reserved 00
0x0A0A A Increment
phase offset
Reserved Reset phase
offset
Decrement
phase offset
Increment
phase offset
00
0x0A0B A Manual
reference
validation
Reserved Force
Timeout B
Force
Timeout A
00
0x0A0C Manual
reference
invalidation
Reserved REF Mon
Override B
REF Mon
Override A
00
0x0A0D Static
reference
validation
Reserved REF Mon
Bypass B
REF Mon
Bypass A
00
Quick In-Out Frequency Soft Pin Configuration
0x0C00 L, E Enable Soft
Pin Section 1
Reserved EN Soft Pin
Section 1
00
0x0C01 L, E Soft Pin
Section 1
Output frequency selection[3:0] Input frequency selection[3:0] 00
0x0C02 L, E Reserved SYSCLK PLL ref sel[1:0] 00
0x0C03
L, E
Enable Soft
Pin Section 2
Reserved
EN Soft Pin
Section 2
00
0x0C04 L, E Soft Pin
Section 2
Reserved REFB frequency scale[1:0] REFA frequency scale[1:0] 00
0x0C05 L, E Reserved Channel 1 output frequency
scale[1:0]
Channel 0 output
frequency scale[1:0]
00
0x0C06
L, E
Reserved
Sel high PM
base loop
filter
DPLL loop BW[1:0]
REF input frequency
tolerance[1:0]
00
0x0C07 L, A,
E
Soft pin
transfer
Reserved Soft pin
start transfer
00
0x0C08 L, E Soft pin
reset
Reserved Soft pin
reset
00