Datasheet

AD9557 Data Sheet
Rev. B | Page 84 of 92
IRQ Monitor (Register 0x0D02 to Register 0x0D07
If not masked via the IRQ mask registers (Register 0x0209 and Register 0x020A), the appropriate IRQ monitor bit is set to Logic 1 when the
indicated event occurs. These bits are cleared only via the IRQ clearing registers (Register 0x0A04 to Register 0A0B), the reset all IRQs bit
(Register 0x0A03[1]), or a device reset.
Table 100. IRQ Monitor for SYSCLK
Address Bits Bit Name Description
0x0D02
[7:6] Reserved Reserved.
5 SYSCLK unlocked Indicates a SYSCLK PLL state transition from locked to unlocked
4
SYSCLK locked Indicates a SYSCLK PLL state transition from unlocked to locked
3
APLL unlocked Indicates an output PLL state transition from locked to unlocked
2 APLL locked Indicates an output PLL state transition from unlocked to locked
1
APLL cal ended Indicates that APLL calibration is complete
0
APLL cal started Indicates that APLL in APLL calibration has begun
Table 101. IRQ Monitor for Distribution Sync, Watchdog Timer and EEPROM
Address Bits Bit Name Description
0x0D03
[7:5] Reserved Reserved
4
Pin program end Indicates successful completion of a ROM load operation
3
Output distribution sync Indicates a distribution sync event
2 Watchdog timer Indicates expiration of the watchdog timer
1
EEPROM fault Indicates a fault during an EEPROM load or save operation
0
EEPROM complete Indicates successful completion of an EEPROM load or save operation
Table 102. IRQ Monitor for the Digital PLL
Address
Bits
Bit Name
Description
0x0D04 7 Switching Indicates that the DPLL is switching to a new reference
6
Closed Indicates that the DPLL has entered closed-loop operation
5
Freerun Indicates that the DPLL has entered free run mode
4 Holdover Indicates that the DPLL has entered holdover mode
3
Frequency unlocked Indicates that the DPLL has lost frequency lock
2
Frequency locked Indicates that the DPLL has acquired frequency lock
1 Phase unlocked Indicates that the DPLL has lost phase lock
0
Phase locked Indicates that the DPLL has acquired phase lock
Table 103. IRQ Monitor for History Update, Frequency Limit and Phase Slew Limit
Address
Bits
Bit Name
Description
0x0D05 [7:5] Reserved Reserved
4 History updated Indicates the occurrence of a tuning word history update
3
Frequency unclamped Indicates a frequency limiter state transition from clamped to unclamped
2
Frequency clamped Indicates a frequency limiter state transition from unclamped to clamped
1 Phase slew unlimited Indicates a phase slew limiter state transition from slew limiting to not slew limiting
0
Phase slew limited Indicates a phase slew limiter state transition from not slew limiting to slew limiting
Table 104. IRQ Monitor for Reference Inputs
Address Bits Bit Name Description
0x0D06
7 Reserved Reserved
6 REFB validated Indicates that REFB has been validated
5
REFB fault cleared Indicates that REFB has been cleared of a previous fault
4
REFB fault Indicates that REFB has been faulted
3
Reserved
Reserved
2 REFA validated Indicates that REFA has been validated
1
REFA fault cleared Indicates that REFA has been cleared of a previous fault
0
REFA fault
Indicates that REFA has been faulted
0x0D07 [7:0] Reserved Reserved