Datasheet

Data Sheet AD9557

Rev. B | Page 91 of 92

Table 125. Multifunction Pin Input Functions (D7 = 0)

0x00

Reserved, high-Z input

0x01

I/O update Register 0x0005, Bit 0

0x02 Full power-down Register 0x0A00, Bit 0

0x03

Clear watchdog Register 0x0A03, Bit 0

0x04 Clear all IRQs Register 0x0A03, Bit 1

0x05

Tuning word history reset Register 0x0A03, Bit 2

0x06 to 0x0E Reserved

0x10

User holdover Register 0x0A01, Bit 6

0x11 User free run Register 0x0A01, Bit 5

0x12

Reset incremental phase offset

0x13 Increment incremental phase offset Register 0x0A0A, Bit 0

0x14

Decrement incremental phase offset Register 0x0A0A, Bit 1

0x15 to 0x1F Reserved

0x20

Override Reference Monitor A Register 0x0A0C, Bit 0

0x21 Override Reference Monitor B Register 0x0A0C, Bit 1

0x22 to 0x2F

Reserved

0x30 Force Validation Timeout A Register 0x0A0B, Bit 0

0x31

Force Validation Timeout B Register 0x0A0B, Bit 1

0x32 to 0x3F Reserved

0x40

Enable OUT0 Register 0x0501, Bit 0

0x41

Enable OUT1

0x42 to 0x45 Reserved

0x46

Enable OUT0 and OUT1 Register 0x0501 and Register 0x0505, Bit 0

0x47 Sync clock distribution outputs Register 0x0A02, Bit 1

0x48 to 0xFF

Reserved