Datasheet

Data Sheet AD9558
Rev. B | Page 15 of 104
Jitter generation (random jitter) uses 19.2 MHz TCXO for system clock input.
Table 18.
Parameter Min Typ Max Unit Test Conditions/Comments
JITTER GENERATION
System clock doubler enabled; high phase
margin mode enabled; Register 0x0405 = 0x20;
Register 0x0403 = 0x07; Register 0x0400 = 0x81;
in cases where multiple driver types are listed,
both driver types were tested at those conditions,
and the one with higher jitter is quoted, although
there is usually not a significant jitter difference
between the driver types
f
REF
= 19.44 MHz; f
OUT
= 644.53 MHz; f
LOOP
= 0.1 Hz
HSTL Driver
Bandwidth: 5 kHz to 20 MHz 402 fs rms
Bandwidth: 12 kHz to 20 MHz
393 fs rms
Bandwidth: 20 kHz to 80 MHz
391 fs rms
Bandwidth: 50 kHz to 80 MHz
347 fs rms
Bandwidth: 16 MHz to 320 MHz
179
fs rms
f
REF
= 19.44 MHz; f
OUT
= 693.48 MHz; f
LOOP
= 0.1 Hz
HSTL Driver
Bandwidth: 5 kHz to 20 MHz
379 fs rms
Bandwidth: 12 kHz to 20 MHz
371 fs rms
Bandwidth: 20 kHz to 80 MHz
371 fs rms
Bandwidth: 50 kHz to 80 MHz
335 fs rms
Bandwidth: 16 MHz to 320 MHz
175 fs rms
f
REF
= 19.44 MHz; f
OUT
= 312.5 MHz; f
LOOP
= 0.1 Hz
HSTL Driver
Bandwidth: 5 kHz to 20 MHz 413 fs rms
Bandwidth: 12 kHz to 20 MHz
404 fs rms
Bandwidth: 20 kHz to 80 MHz
407 fs rms
Bandwidth: 50 kHz to 80 MHz
358 fs rms
Bandwidth: 4 MHz to 80 MHz
142 fs rms
f
REF
= 25 MHz; f
OUT
= 161.1328 MHz; f
LOOP
= 0.1 Hz
HSTL Driver
Bandwidth: 5 kHz to 20 MHz
399
fs rms
Bandwidth: 12 kHz to 20 MHz 391 fs rms
Bandwidth: 20 kHz to 80 MHz
414 fs rms
Bandwidth: 50 kHz to 80 MHz
376 fs rms
Bandwidth: 4 MHz to 80 MHz
190 fs rms
f
REF
= 2 kHz; f
OUT
= 70.656 MHz; f
LOOP
= 0.1 Hz
HSTL and/or 3.3 V CMOS Driver
Bandwidth: 10 Hz to 30 MHz
970 fs rms
Bandwidth: 12 kHz to 20 MHz
404 fs rms
Bandwidth: 10 kHz to 400 kHz
374 fs rms
Bandwidth: 100 kHz to 10 MHz
281 fs rms