Datasheet

Data Sheet AD9558
Rev. B | Page 25 of 104
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
AD9557/
AD9558
HSTL OR
LVDS
DOWNSTREAM
DEVICE
WITH HIGH
IMPEDANCE
INPUT AND
INTERNAL
DC BIAS
0.1µF
0.1µF
100Ω
09758-130
Figure 30. AC-Coupled LVDS or HSTL Output Driver
(100 Ω resistor can go on either side of decoupling capacitors and should be
as close as possible to the destination receiver.)
AD9557/
AD9558
HSTL OR
LVDS
Z
0
= 50Ω
Z
0
= 50Ω
SINGLE-ENDED
(NOT COUPLED)
LVDS OR 1.8V HSTL
HIGH IMPEDANCE
DIFFERENTIAL
RECEIVER
100Ω
09758-131
Figure 31. DC-Coupled LVDS or HSTL Output Driver
SINGLE-ENDED
(NOT COUPLED)
V
S
= 3.3V
3.3V
LVPECL
82Ω82Ω
127Ω127Ω
0.1µF
0.1µF
AD9557/
AD9558
1.8V
HSTL
Z
0
= 50Ω
Z
0
= 50Ω
09758-132
Figure 32. Interfacing the HSTL Driver to a 3.3 V LVPECL Input
(This method incorporates impedance matching and dc biasing for bipolar
LVPECL receivers. If the receiver is self-biased, the termination scheme shown
in Figure 30 is recommended.)
XOA
XOB
AD9557/
AD9558
10MHz TO 50MHz FUNDAMENTAL
AT CUT CRYSTAL WITH
10pF LOAD CAPACITANCE
10pF
10pF
09758-133
Figure 33. System Clock Input (XOA, XOB) in Crystal Mode
(The recommended C
LOAD
= 10 pF is shown. The values of the 10 pF shunt
capacitors shown here should equal the C
LOAD
of the crystal.)
XOA
300Ω
150Ω
0.1µF
XOB
AD9557/
AD9558
3.3V
CMOS
TCXO
0.1µF
09758-134
Figure 34. System Clock Input (XOA, XOB) When Using a TCXO/OCXO with
3.3 V CMOS Output