Datasheet

AD9558 Data Sheet
Rev. B | Page 38 of 104
CLOCK DISTRIBUTION
FROM APLL
(3.35GHz TO 4.05GHz)
09758-139
÷M1
OUT1
1
OUT1
1
OUT2
1
OUT2
1
MAX
1.25GHz
MAX
1.25GHz
÷M2
RF
DIVIDER 1
÷3
T
O ÷1
1
RF
DIVIDER 2
÷3 TO ÷11
FRAME SYNC
MODE ONLY
÷M0
OUT0
1
OUT0
1
÷M3
OUT4
1
OUT4
1
OUT3
1
OUT3
1
÷M3b
OUT5
1
OUT5
1
×2
OUT0, OUT1, OUT2, OUT3, OUT4: 360kHz
TO 1.25GHz; OUT5: 352Hz T
O 1.25GHz.
CHANNEL
SYNC
BLOCK
FRAME
SYNC
BLOCK
CHIP RESET
SELECTED INPUT FRAME PULSE
SYNC SIGNAL TO
M0 TO M3 DIVIDERS
FRAME SYNC
FRAME SYNC ENGAGED SIGNAL
FRAME
SYNC
MONITOR
SYNC/SOFT_SYNC
Fsync_ALIGN_METHOD
Figure 40. Clock Distribution Block Diagram
CLOCK DIVIDERS
The channel divider blocks, M0, M1, M2, M3, and M3b, are
10-bit integer dividers with a divide range of 1 to 1023. The
channel divider block contains duty cycle correction that
guarantees 50% duty cycle for both even and odd divide ratios.
OUTPUT POWER-DOWN
The output drivers can be individually powered down.
OUTPUT ENABLE
Each of the output channels offers independent control of enable/
disable functionality via the distribution enable register. The
distribution outputs use synchronization logic to control
enable/disable activity to avoid the production of runt pulses
and ensure that outputs with the same divide ratios become
active/inactive in unison.
OUTPUT MODE
The user has independent control of the operating mode of each of
the four output channels via the output clock distribution registers
(Address 0x0500 to Address 0x0515). The operating mode
control includes
• Logic family and pin functionality
• Output drive strength
• Output polarity
• Divide ratio
• Phase of each output channel
Channel 0 and Channel 3 provide 3.3 V CMOS, in addition
to 1.8 V CMOS modes. Channel 1 and Channel 2 have 1.8 V
CMOS, LVDS, and HSTL modes.
All CMOS drivers feature a CMOS drive strength that allows
the user to choose between a strong, high performance CMOS
driver, or a lower power setting with less EMI and crosstalk.
The best setting is application dependent.
For applications where LVPECL levels are required, the user
should choose the HSTL mode, and ac-couple the output signal.
See the Input/Output Termination Recommendations section
for recommended termination schemes.
CLOCK DISTRIBUTION SYNCHRONIZATION
Divider Synchronization
The dividers in the clock distribution channels can be
synchronized with each other.
At power-up, the clock dividers are held static until a sync signal
is initiated by the channel SYNC block. The following are
possible sources of a SYNC signal, and these settings are found
in Register 0x0500:
• Direct sync via Bit 2 of Register 0x0500
• Direct sync via a sync op code (0xA1) in the EEPROM
storage sequence during EEPROM loading
• DPLL phase or frequency lock
• A rising edge of the selected reference input
• The A
SYNC
E
A
pin
• A multifunction pin configured for the SYNC signal
The APLL lock detect signal gates the SYNC signal from the
channel sync block shown in Figure 40. The channel dividers
receive a SYNC signal from the channel SYNC block only if the
APLL is calibrated and locked, unless the APLL locked
controlled sync bit (Register 0x0405[3]) is set.