Datasheet

Data Sheet AD9558
Rev. B | Page 49 of 104
SERIAL CONTROL PORT
The AD9558 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to
many industry-standard microcontrollers and microprocessors.
The AD9558 serial control port is compatible with most
synchronous transfer formats, including I²C, Motorola SPI, and
Intel SSR protocols. The serial control port allows read/write
access to the AD9558 register map.
In SPI mode, single or multiple byte transfers are supported.
The SPI port configuration is programmable via Register 0x0000.
This register is integrated into the SPI control logic rather than
in the register map and is distinct from the I
2
C Register 0x0000.
It is also inaccessible to the EEPROM controller.
Although the AD9558 supports both the SPI and I
2
C serial port
protocols, only one or the other is active following power-up (as
determined by the M0 and M1 multifunction pins during the
startup sequence). That is, the only way to change the serial port
protocol is to reset the device (or cycle the device power supply).
SPI/I²C PORT SELECTION
Because the AD9558 supports both SPI and I²C protocols, the
active serial port protocol depends on the logic state of the
PINCONTROL, M1, and M0 pins. The PINCONTROL pin
must be low, and the state of the M0 and M1 pins determines
the I
2
C address, or if SPI mode is enabled. See Table 24 for the
I
2
C address assignments.
Table 24. SPI/I²C Serial Port Setup
M1 M0 SPI/I²C
Low Low SPI
Low Open I²C, 1101000
Low High I²C, 1101001
Open
Low
I²C, 1101010
Open Open I²C, 1101011
Open High I²C, 1101100
High Low I²C, 1101101
High Open I²C, 1101110
High High I²C, 1101111
SPI SERIAL PORT OPERATION
Pin Descriptions
The SCLK (serial clock) pin serves as the serial shift clock. This
pin is an input. SCLK synchronizes serial control port read and
write operations. The rising edge SCLK registers write data bits,
and the falling edge registers read data bits. The SCLK pin
supports a maximum clock rate of 40 MHz.
The SDIO (serial data input/output) pin is a dual-purpose pin
and acts as either an input only (unidirectional mode) or as
both an input and an output (bidirectional mode). The AD9558
default SPI mode is bidirectional.
The SDO (serial data output) pin is useful only in unidirectional
I/O mode. It serves as the data output pin for read operations.
The
EE
AA
(chip select) pin is an active low control that gates read
and write operations. This pin is internally connected to a 30 kΩ
pull-up resistor. When
AA
CS
EE
AA
is high, the SDO and SDIO pins go
into a high impedance state.
CS
SPI Mode Operation
The SPI port supports both 3-wire (bidirectional) and 4-wire
(unidirectional) hardware configurations and both MSB-first
and LSB-first data formats. Both the hardware configuration
and data format features are programmable. By default, the
AD9558 uses the bidirectional MSB-first mode. The reason that
bidirectional is the default mode is so that the user can still
write to the device, if it is wired for unidirectional operation, to
switch to unidirectional mode.
Assertion (active low) of the AA
CS
EE
AA
pin initiates a write or read
operation to the
AD9558 SPI port. For data transfers of three
bytes or fewer (excluding the instruction word), the device
supports the
AA
CS
EE
AA
stalled high mode (see Table 25). In this mode,
the
AA
CS
EE
AA
pin can be temporarily deasserted on any byte boundary,
allowing time for the system controller to process the next byte.
AA
CS
EE
AA
can be deasserted only on byte boundaries, however. This
applies to both the instruction and data portions of the transfer.
During stall high periods, the serial control port state machine
enters a wait state until all data is sent. If the system controller
decides to abort a transfer midstream, then the state machine must
be reset either by completing the transfer or by asserting the
AA
CS
EE
AA
pin for at least one complete SCLK cycle (but less than eight
SCLK cycles). Deasserting the
AA
CS
EE
AA
pin on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 25), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented.
AA
CS
EE
AA
must be deasserted
at the end of the last byte that is transferred, thereby ending the
streaming mode.
Table 25. Byte Transfer Count
W1 W0 Bytes to Transfer
0
0 1
0
1 2
1
0 3
1
1 Streaming mode
Communication Cycle—Instruction Plus Data
The SPI protocol consists of a two-part communication cycle.
The first part is a 16-bit instruction word that is coincident with
the first 16 SCLK rising edges and a payload. The instruction
word provides the AD9558
serial control port with information
regarding the payload. The instruction word includes the R/
AA
W
EE
AA
bit that indicates the direction of the payload transfer (that is, a
read or write operation). The instruction word also indicates
the number of bytes in the payload and the starting register
address of the first payload byte.